e16-Co502-RISCV-Pipeline-CPU-Implimentation

This is the RISC-V ISA implementation by Group 2
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Table of Contents

1. About The Project
   • Built With
2. Getting Started
   • Installation
3. Usage
4. License
5. Contact
6. Acknowledgements

About The Project

This is the RISC-V CPU implimentation using VERILOG_HDL.

Built With

• VERILOG HDL
• C++

Getting Started

To get a local copy up and running follow these simple steps.

Installation

1. Clone the repo

   git clone https://github.com/github_username/repo_name.git

2. Install Verilog

   sudo apt-get install iverilog

3. Install GDKwave

   sudo apt install gtkwave

Usage

1. Navigate to folder

        cd CPU\ Testbench

2. Compile

        iverilog -o group2cpu.vvp RiscV_TB.v

3. Run

        vvp group2cpu.vvp

4. Open with GTKwave tool

        gtkwave cpu_wavedata.vcd

This is tested with the verilog compiler version 10.3

License

Distributed under the MIT License. See LICENSE for more information.

Contact

Isuru Lakshan - @isuru - email Randika viraj - @randika - email

Project Link: https://github.com/cepdnaclk/e16-co502-RISCV-Pipeline-CPU-Implimentation-Group2

Acknowledgements

• Dr. Isuru Nawinne
• Dr. Mahanama Wickramasinghe