Single-Cycle-Risc-V-32I

This repo contains Single cycle Risc V 32I processor on verilog.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Fetch.out		Fetch.out
Fetch.v		Fetch.v
README.md		README.md
imm_gen.out		imm_gen.out
imm_gen.v		imm_gen.v
instruct.mem		instruct.mem
instructionmem.v		instructionmem.v
memory.out		memory.out
memory.v		memory.v
mux.out		mux.out
mux.v		mux.v
mux2.v		mux2.v
mux3.v		mux3.v
pc.v		pc.v
register.out		register.out
register.v		register.v
register_tb.v		register_tb.v
top.vcd		top.vcd
typedecode.out		typedecode.out
typedecode.v		typedecode.v
typedecode.vcd		typedecode.vcd
typedecode_tb.v		typedecode_tb.v
wrapmem.v		wrapmem.v
write_back.out		write_back.out
write_back.v		write_back.v

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