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mazhar-update-p1
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@mazharali09
mazharali09 committed Sep 8, 2023
1 parent a44cd9f commit 5a2fe13
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Showing 6 changed files with 41 additions and 23 deletions.
5 changes: 2 additions & 3 deletions core/alu.sv
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Expand Up @@ -280,12 +280,11 @@ module alu import ariane_pkg::*; #(
BSET, BSETI: result_o = fu_data_i.operand_a | bit_indx;

// Count Leading/Trailing Zeros
CLZ, CTZ : result_o = (lz_tz_empty) ? ({{(riscv::XLEN-$bits(lz_tz_count)){1'b0}},lz_tz_count} + 1) : ({{(riscv::XLEN-$bits(lz_tz_count)){1'b0}},lz_tz_count});

CLZ, CTZ : result_o = (lz_tz_empty) ? (lz_tz_count + 1) : lz_tz_count;
CLZW, CTZW: result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN-5{1'b0}}, lz_tz_wcount};

// Count population
CPOP, CPOPW: result_o = {{(riscv::XLEN-($clog2(riscv::XLEN))){1'b0}}, cpop};
CPOP, CPOPW: result_o = {{(riscv::XLEN-(($clog2(riscv::XLEN) +1))){1'b0}}, cpop};

// Sign and Zero Extend
SEXTB: result_o = {{riscv::XLEN-8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]};
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6 changes: 3 additions & 3 deletions core/cache_subsystem/cva6_icache.sv
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Expand Up @@ -118,15 +118,15 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign cl_tag_d = (areq_i.fetch_valid) ? areq_i.fetch_paddr[ICACHE_TAG_WIDTH+ICACHE_INDEX_WIDTH-1:ICACHE_INDEX_WIDTH] : cl_tag_q;

// noncacheable if request goes to I/O space, or if cache is disabled
assign paddr_is_nc = (~cache_en_q) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{{64-riscv::PLEN}{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));
assign paddr_is_nc = (~cache_en_q) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{64-riscv::PLEN{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));

// pass exception through
assign dreq_o.ex = areq_i.fetch_exception;

// latch this in case we have to stall later on
// make sure this is 32bit aligned
assign vaddr_d = (dreq_o.ready & dreq_i.req) ? dreq_i.vaddr : vaddr_q;
assign areq_o.fetch_vaddr = {vaddr_q>>2, 2'b0};
assign areq_o.fetch_vaddr = {vaddr_q[riscv::VLEN-1:2], 2'b0};

// split virtual address into index and offset to address cache arrays
assign cl_index = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH];
Expand Down Expand Up @@ -166,7 +166,7 @@ end else begin : gen_piton_offset
// main control logic
///////////////////////////////////////////////////////
logic addr_ni;
assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, {{64-$bits(areq_i.fetch_paddr){1'b0}},areq_i.fetch_paddr});
assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, areq_i.fetch_paddr);
always_comb begin : p_fsm
// default assignment
state_d = state_q;
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24 changes: 22 additions & 2 deletions core/cache_subsystem/wt_dcache_wbuffer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -191,15 +191,35 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
toSize32(bdirty[dirty_ptr]);

// replicate transfers shorter than a dword
/*
always_comb begin
if (riscv::IS_XLEN64)
miss_wdata_o = repData64(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]);
else
miss_wdata_o = repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]);
end*/
assign miss_wdata_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]):
repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]);
repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]);

if (ariane_pkg::DATA_USER_EN) begin
/*
if (riscv::IS_XLEN64)
assign miss_wuser_o = repData64(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);
else
assign miss_wuser_o = repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);
*/
assign miss_wuser_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]):
repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);
repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);
end else begin
assign miss_wuser_o = '0;
end

/*
if (riscv::IS_XLEN64)
assign tx_be = to_byte_enable8(bdirty_off, miss_size_o[1:0]);
else
assign tx_be = to_byte_enable4(bdirty_off, miss_size_o[1:0]);
*/
assign tx_be = riscv::IS_XLEN64 ? to_byte_enable8(bdirty_off, miss_size_o[1:0]):
to_byte_enable4(bdirty_off, miss_size_o[1:0]);

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4 changes: 2 additions & 2 deletions core/frontend/instr_queue.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -279,8 +279,8 @@ module instr_queue import ariane_pkg::*; #(
end
fetch_entry_o.instruction = instr_data_out[i].instr;
fetch_entry_o.ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
fetch_entry_o.ex.tval = {{64-riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
fetch_entry_o.branch_predict.cf = instr_data_out[i].cf;
fetch_entry_o.ex.tval = {/*{64-riscv::VLEN{1'b0}},*/ instr_data_out[i].ex_vaddr};
fetch_entry_o.branch_predict.cf = instr_data_out[i].cf;
pop_instr[i] = fetch_entry_valid_o & fetch_entry_ready_i;
end
end
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15 changes: 7 additions & 8 deletions core/issue_read_operands.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -83,8 +83,8 @@ module issue_read_operands import ariane_pkg::*; #(
);
logic stall;
logic fu_busy; // functional unit is busy
riscv::xlen_t operand_a_regfile, operand_b_regfile; // operands coming from regfile
rs3_len_t operand_c_regfile; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3
riscv::xlen_t operand_a_regfile, operand_b_regfile, operand_c_regfile; // operands coming from regfile
//rs3_len_t operand_c_regfile; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3
// output flipflop (ID <-> EX)
riscv::xlen_t operand_a_n, operand_a_q,
operand_b_n, operand_b_q,
Expand Down Expand Up @@ -219,11 +219,10 @@ module issue_read_operands import ariane_pkg::*; #(
// immediates are the third operands in the store case
// for FP operations, the imm field can also be the third operand from the regfile
if (CVA6Cfg.NrRgprPorts == 3) begin
imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} :
issue_instr_i.op == OFFLOAD ? {{(riscv::XLEN-$bits(operand_c_regfile)){1'b0}},operand_c_regfile} : issue_instr_i.result;

imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {/*{riscv::XLEN-CVA6Cfg.FLen{1'b0}},*/ operand_c_regfile} :
issue_instr_i.op == OFFLOAD ? operand_c_regfile : issue_instr_i.result;
end else begin
imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.result;
imm_n = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {/*{riscv::XLEN-CVA6Cfg.FLen{1'b0}},*/ operand_c_regfile} : issue_instr_i.result;
end
trans_id_n = issue_instr_i.trans_id;
fu_n = issue_instr_i.fu;
Expand All @@ -238,7 +237,7 @@ module issue_read_operands import ariane_pkg::*; #(
end

if (forward_rs3) begin
imm_n = CVA6Cfg.NrRgprPorts == 3 ? {{(riscv::XLEN-$bits(rs3_i)){1'b0}},rs3_i} : {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, rs3_i};;
imm_n = CVA6Cfg.NrRgprPorts == 3 ? rs3_i : {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, rs3_i};;
end

// use the PC as operand a
Expand Down Expand Up @@ -500,7 +499,7 @@ module issue_read_operands import ariane_pkg::*; #(
assign operand_a_regfile = is_rs1_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[0]} : rdata[0];
assign operand_b_regfile = is_rs2_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[1]} : rdata[1];
assign operand_c_regfile = CVA6Cfg.NrRgprPorts == 3 ? (is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[2]} : rdata[2])
: fprdata[2];
: {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[2]} ;

// ----------------------
// Registers (ID <-> EX)
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10 changes: 5 additions & 5 deletions corev_apu/tb/common/mock_uart.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -62,11 +62,11 @@ module mock_uart (
if (psel_i & penable_i & pwrite_i) begin
case ((paddr_i >> 'h2) & 'h7)
THR: begin
if (lcr & 'h80) dll <= byte'(pwdata_i[7:0]);
if (&(lcr & 'h80)) dll <= byte'(pwdata_i[7:0]);
else uart_tx(byte'(pwdata_i[7:0]));
end
IER: begin
if (lcr & 'h80) dlm <= byte'(pwdata_i[7:0]);
if (&(lcr & 'h80)) dlm <= byte'(pwdata_i[7:0]);
else ier <= byte'(pwdata_i[7:0] & 'hF);
end
FCR: begin
Expand All @@ -89,10 +89,10 @@ module mock_uart (
if (psel_i & penable_i & ~pwrite_i) begin
case ((paddr_i >> 'h2) & 'h7)
THR: begin
if (lcr & 'h80) prdata_o = {24'b0, dll};
if (&(lcr & 'h80)) prdata_o = {24'b0, dll};
end
IER: begin
if (lcr & 'h80) prdata_o = {24'b0, dlm};
if (&(lcr & 'h80)) prdata_o = {24'b0, dlm};
else prdata_o = {24'b0, ier};
end
IIR: begin
Expand All @@ -101,7 +101,7 @@ module mock_uart (
end
LCR: prdata_o = {24'b0, lcr};
MCR: prdata_o = {24'b0, mcr};
LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))};
LSR: prdata_o = {24'b0, (lsr | (8'b00000001 << THRE) | (8'b00000001 << TEMT))};
MSR: prdata_o = {24'b0, msr};
SCR: prdata_o = {24'b0, scr};
default:;
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