WIDTHEXPAND 1st Priority warnings resolved

10x-Engineers · Sep 8, 2023 · a44cd9f · fatimasaleem · Sep 9, 2023 · gullahmed1
1 parent 983d6cb
commit a44cd9f
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Showing 12 changed files with 33 additions and 31 deletions.
diff --git a/core/alu.sv b/core/alu.sv
@@ -280,7 +280,8 @@ module alu import ariane_pkg::*; #(
                 BSET, BSETI: result_o = fu_data_i.operand_a | bit_indx;
 
                 // Count Leading/Trailing Zeros
-                CLZ, CTZ  :  result_o = (lz_tz_empty) ? (lz_tz_count + 1) : lz_tz_count;
+                CLZ, CTZ  :  result_o = (lz_tz_empty) ? ({{(riscv::XLEN-$bits(lz_tz_count)){1'b0}},lz_tz_count} + 1) : ({{(riscv::XLEN-$bits(lz_tz_count)){1'b0}},lz_tz_count});
+
                 CLZW, CTZW:  result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN-5{1'b0}}, lz_tz_wcount};
 
                 // Count population

diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv
@@ -166,7 +166,7 @@ end else begin : gen_piton_offset
 // main control logic
 ///////////////////////////////////////////////////////
   logic addr_ni;
-  assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, areq_i.fetch_paddr);
+  assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, {{64-$bits(areq_i.fetch_paddr){1'b0}},areq_i.fetch_paddr});
   always_comb begin : p_fsm
     // default assignment
     state_d      = state_q;

diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -271,7 +271,7 @@ module csr_regfile import ariane_pkg::*; #(
                 riscv::CSR_MARCHID:            csr_rdata = ARIANE_MARCHID;
                 riscv::CSR_MIMPID:             csr_rdata = '0; // not implemented
                 riscv::CSR_MHARTID:            csr_rdata = hart_id_i;
-                riscv::CSR_MCOUNTINHIBIT:      csr_rdata = mcountinhibit_q;
+                riscv::CSR_MCOUNTINHIBIT:      csr_rdata = {{riscv::XLEN-$bits(mcountinhibit_q){1'b0}},mcountinhibit_q};
                 // Counters and Timers
                 riscv::CSR_MCYCLE:             csr_rdata = cycle_q[riscv::XLEN-1:0];
                 riscv::CSR_MCYCLEH:            if (riscv::XLEN == 32) csr_rdata = cycle_q[63:32]; else read_access_exception = 1'b1;
@@ -467,7 +467,7 @@ module csr_regfile import ariane_pkg::*; #(
                 riscv::CSR_PMPADDR14,
                 riscv::CSR_PMPADDR15: begin
                     // index is specified by the last byte in the address
-                    index = csr_addr.csr_decode.address[3:0];
+                    index = {{28{1'b0}},csr_addr.csr_decode.address[3:0]};
                     // Important: we only support granularity 8 bytes (G=1)
                     // -> last bit of pmpaddr must be set 0/1 based on the mode:
                     // NA4, NAPOT: 1
@@ -692,7 +692,7 @@ module csr_regfile import ariane_pkg::*; #(
                     if (!CVA6Cfg.RVV) begin
                         mstatus_d.vs = riscv::Off;
                     end
-                    mstatus_d.wpri3 = 8'b0;
+                    mstatus_d.wpri3 = 9'b0;
                     mstatus_d.wpri1 = 1'b0;
                     mstatus_d.wpri2 = 1'b0;
                     mstatus_d.wpri0  = 1'b0;
@@ -884,7 +884,7 @@ module csr_regfile import ariane_pkg::*; #(
                 riscv::CSR_PMPADDR14,
                 riscv::CSR_PMPADDR15:  begin
                     // index is specified by the last byte in the address
-                    automatic int index = csr_addr.csr_decode.address[3:0];
+                    automatic int index = {{28{1'b0}},csr_addr.csr_decode.address[3:0]};
                     // check if the entry or the entry above is locked
                     if (!pmpcfg_q[index].locked && !(pmpcfg_q[index+1].locked && pmpcfg_q[index].addr_mode == riscv::TOR)) begin
                         pmpaddr_d[index] = csr_wdata[riscv::PLEN-3:0];
@@ -1219,7 +1219,7 @@ module csr_regfile import ariane_pkg::*; #(
     // ----------------------
     always_comb begin : exception_ctrl
         csr_exception_o = {
-            '0, '0, 1'b0
+           {(2*riscv::XLEN-2){1'b0}}, '0, '0, 1'b0
         };
         // ----------------------------------
         // Illegal Access (decode exception)
@@ -1301,11 +1301,11 @@ module csr_regfile import ariane_pkg::*; #(
         csr_rdata_o = csr_rdata;
 
         unique case (csr_addr.address)
-            riscv::CSR_MIP: csr_rdata_o = csr_rdata | (irq_i[1] << riscv::IRQ_S_EXT);
+            riscv::CSR_MIP: csr_rdata_o = csr_rdata | ({{riscv::XLEN-1{1'b0}},irq_i[1]} << riscv::IRQ_S_EXT);
             // in supervisor mode we also need to check whether we delegated this bit
             riscv::CSR_SIP: begin
                 csr_rdata_o = csr_rdata
-                            | ((irq_i[1] & mideleg_q[riscv::IRQ_S_EXT]) << riscv::IRQ_S_EXT);
+                            | (({{riscv::XLEN-1{1'b0}},irq_i[1]} & {{riscv::XLEN-1{1'b0}},mideleg_q[riscv::IRQ_S_EXT]}) << riscv::IRQ_S_EXT);
             end
             default:;
         endcase
@@ -1386,8 +1386,8 @@ module csr_regfile import ariane_pkg::*; #(
             stval_q                <= {riscv::XLEN{1'b0}};
             satp_q                 <= {riscv::XLEN{1'b0}};
             // timer and counters
-            cycle_q                <= {riscv::XLEN{1'b0}};
-            instret_q              <= {riscv::XLEN{1'b0}};
+            cycle_q                <= {{64-riscv::XLEN{1'b0}},{riscv::XLEN{1'b0}}};
+            instret_q              <= {{64-riscv::XLEN{1'b0}},{riscv::XLEN{1'b0}}};
             // aux registers
             en_ld_st_translation_q <= 1'b0;
             // wait for interrupt

diff --git a/core/instr_realign.sv b/core/instr_realign.sv
@@ -97,7 +97,7 @@ module instr_realign import ariane_pkg::*; #(
                     unaligned_instr_d = data_i[15:0];
                 // the instruction isn't compressed but only the lower is ready
                 end else begin
-                    valid_o = 1'b1;
+                    valid_o = {{$bits(valid_o)-1{1'b0}},1'b1};
                 end
             end
         end

diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv
@@ -220,7 +220,8 @@ module issue_read_operands import ariane_pkg::*; #(
         // for FP operations, the imm field can also be the third operand from the regfile
         if (CVA6Cfg.NrRgprPorts == 3) begin
             imm_n  = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} :
-                                                    issue_instr_i.op == OFFLOAD ? operand_c_regfile : issue_instr_i.result;
+                                                    issue_instr_i.op == OFFLOAD ? {{(riscv::XLEN-$bits(operand_c_regfile)){1'b0}},operand_c_regfile} : issue_instr_i.result;
+
         end else begin
             imm_n  = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.result;
         end
@@ -237,7 +238,7 @@ module issue_read_operands import ariane_pkg::*; #(
         end
 
         if (forward_rs3) begin
-            imm_n  = CVA6Cfg.NrRgprPorts == 3 ? rs3_i : {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, rs3_i};;
+            imm_n  = CVA6Cfg.NrRgprPorts == 3 ? {{(riscv::XLEN-$bits(rs3_i)){1'b0}},rs3_i} : {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, rs3_i};;
         end
 
         // use the PC as operand a

diff --git a/core/load_unit.sv b/core/load_unit.sv
@@ -176,7 +176,7 @@ module load_unit import ariane_pkg::*; #(
     logic not_commit_time;
     logic inflight_stores;
     logic stall_ni;
-    assign paddr_ni = is_inside_nonidempotent_regions(ArianeCfg, {dtlb_ppn_i,12'd0});
+    assign paddr_ni = is_inside_nonidempotent_regions(ArianeCfg, {{52-$bits(dtlb_ppn_i){1'b0}},{dtlb_ppn_i,12'd0}});
     assign not_commit_time = commit_tran_id_i != lsu_ctrl_i.trans_id;
     assign inflight_stores = (!dcache_wbuffer_not_ni_i || !store_buffer_empty_i);
     assign stall_ni = (inflight_stores || not_commit_time) && paddr_ni;

diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv
@@ -390,7 +390,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #(
             lsu_dtlb_ppn_o        = {{riscv::PLEN-riscv::VLEN{1'b0}},lsu_vaddr_n[riscv::VLEN-1:12]};
         end else begin
             lsu_paddr_o           = lsu_vaddr_q[riscv::PLEN-1:0];
-            lsu_dtlb_ppn_o        = lsu_vaddr_n[riscv::VLEN-1:12];
+            lsu_dtlb_ppn_o        = {{$bits(lsu_dtlb_ppn_o)-$bits(lsu_vaddr_n[riscv::VLEN-1:12]){1'b0}},lsu_vaddr_n[riscv::VLEN-1:12]};
         end
         lsu_valid_o           = lsu_req_q;
         lsu_exception_o       = misaligned_ex_q;

diff --git a/core/pmp/src/pmp_entry.sv b/core/pmp/src/pmp_entry.sv
@@ -33,7 +33,7 @@ module pmp_entry #(
     logic [PLEN-1:0] base;
     logic [PLEN-1:0] mask;
     int unsigned size;
-    assign conf_addr_n = ~conf_addr_i;
+    assign conf_addr_n = {{PLEN-PMP_LEN{1'b0}},~conf_addr_i};
     lzc #(.WIDTH(PLEN), .MODE(1'b0)) i_lzc(
         .in_i    ( conf_addr_n ),
         .cnt_o   ( trail_ones  ),
@@ -48,15 +48,15 @@ module pmp_entry #(
                 size = '0;
                 // check that the requested address is in between the two
                 // configuration addresses
-                if (addr_i >= (conf_addr_prev_i << 2) && addr_i < (conf_addr_i << 2)) begin
+                if (addr_i >= ({{PLEN-PMP_LEN{1'b0}},conf_addr_prev_i} << 2) && addr_i < ({{PLEN-PMP_LEN{1'b0}},conf_addr_i} << 2)) begin
                     match_o = 1'b1;
                 end else match_o = 1'b0;
 
                 // synthesis translate_off
                 if (match_o == 0) begin
-                    assert(addr_i >= (conf_addr_i << 2) || addr_i < (conf_addr_prev_i << 2));
+                    assert(addr_i >= ({{PLEN-PMP_LEN{1'b0}},conf_addr_i} << 2) || addr_i < ({{PLEN-PMP_LEN{1'b0}},conf_addr_prev_i} << 2));
                 end else begin
-                    assert(addr_i < (conf_addr_i << 2) && addr_i >= (conf_addr_prev_i << 2));
+                    assert(addr_i < ({{PLEN-PMP_LEN{1'b0}},conf_addr_i} << 2) && addr_i >= ({{PLEN-PMP_LEN{1'b0}},conf_addr_prev_i} << 2));
                 end
                 // synthesis translate_on
 
@@ -66,11 +66,11 @@ module pmp_entry #(
                 if (conf_addr_mode_i == riscv::NA4) size = 2;
                 else begin
                     // use the extracted trailing ones
-                    size = trail_ones+3;
+                    size = {{32-$bits(trail_ones){1'b0}},trail_ones}+3;
                 end
 
                 mask = '1 << size;
-                base = (conf_addr_i << 2) & mask;
+                base = ({{PLEN-PMP_LEN{1'b0}},conf_addr_i} << 2) & mask;
                 match_o = (addr_i & mask) == base ? 1'b1 : 1'b0;
 
                 // synthesis translate_off

diff --git a/core/scoreboard.sv b/core/scoreboard.sv
@@ -176,7 +176,7 @@ module scoreboard #(
         // save the target address of a branch (needed for debug in commit stage)
         mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
         if (mem_n[trans_id_i[i]].sbe.fu == ariane_pkg::CVXIF && ~x_we_i) begin
-          mem_n[trans_id_i[i]].sbe.rd = 5'b0;
+          mem_n[trans_id_i[i]].sbe.rd = 6'b0;
         end
         // write the exception back if it is valid
         if (ex_i[i].valid)
@@ -215,7 +215,7 @@ module scoreboard #(
   // FIFO counter updates
   assign num_commit = (CVA6Cfg.NrCommitPorts == 2) ? commit_ack_i[1] + commit_ack_i[0] : commit_ack_i[0];
 
-  assign issue_cnt_n         = (flush_i) ? '0 : issue_cnt_q         - num_commit + issue_en;
+  assign issue_cnt_n         = (flush_i) ? '0 : issue_cnt_q - {{3-$bits(num_commit){1'b0}},num_commit} + {{3-$bits(issue_en){1'b0}},issue_en};
   assign commit_pointer_n[0] = (flush_i) ? '0 : commit_pointer_q[0] + num_commit;
   assign issue_pointer_n     = (flush_i) ? '0 : issue_pointer_q     + issue_en;
 

diff --git a/core/serdiv.sv b/core/serdiv.sv
@@ -107,8 +107,8 @@ module serdiv import ariane_pkg::*; #(
     .empty_o ( lzc_b_no_one )
   );
 
-  assign shift_a      = (lzc_a_no_one) ? WIDTH : lzc_a_result;
-  assign div_shift    = lzc_b_result - shift_a;
+  assign shift_a      = (lzc_a_no_one) ? WIDTH : {{$bits(shift_a)-$bits(lzc_a_result){1'b0}},lzc_a_result};
+  assign div_shift    = {{$bits(div_shift)-$bits(lzc_b_result){1'b0}},lzc_b_result} - shift_a;
 
   assign op_b         = op_b_i <<< $unsigned(div_shift);
 

diff --git a/core/store_buffer.sv b/core/store_buffer.sv
@@ -78,7 +78,7 @@ module store_buffer import ariane_pkg::*; #(
         speculative_status_cnt = speculative_status_cnt_q;
 
         // we are ready if the speculative and the commit queue have a space left
-        ready_o = (speculative_status_cnt_q < (DEPTH_SPEC - 1)) || commit_i;
+        ready_o = ({{$bits(DEPTH_SPEC)-$bits(speculative_status_cnt_q){1'b0}},speculative_status_cnt_q} < (DEPTH_SPEC - 1)) || commit_i;
         // default assignments
         speculative_status_cnt_n    = speculative_status_cnt_q;
         speculative_read_pointer_n  = speculative_read_pointer_q;
@@ -149,7 +149,7 @@ module store_buffer import ariane_pkg::*; #(
         automatic logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt;
         commit_status_cnt = commit_status_cnt_q;
 
-        commit_ready_o = (commit_status_cnt_q < DEPTH_COMMIT);
+        commit_ready_o = ({{$bits(DEPTH_COMMIT)-$bits(commit_status_cnt_q){1'b0}},commit_status_cnt_q} < DEPTH_COMMIT);
         // no store is pending if we don't have any element in the commit queue e.g.: it is empty
         no_st_pending_o         = (commit_status_cnt_q == 0);
         // default assignments
@@ -268,15 +268,15 @@ module store_buffer import ariane_pkg::*; #(
         else $error ("[Commit Queue] You are trying to commit and flush in the same cycle");
 
     speculative_buffer_overflow: assert property (
-        @(posedge clk_i) rst_ni && (speculative_status_cnt_q == DEPTH_SPEC) |-> !valid_i)
+        @(posedge clk_i) rst_ni && ({{32-$bits(speculative_status_cnt_q){1'b0}},speculative_status_cnt_q} == DEPTH_SPEC) |-> !valid_i)
         else $error ("[Speculative Queue] You are trying to push new data although the buffer is not ready");
 
     speculative_buffer_underflow: assert property (
         @(posedge clk_i) rst_ni && (speculative_status_cnt_q == 0) |-> !commit_i)
         else $error ("[Speculative Queue] You are committing although there are no stores to commit");
 
     commit_buffer_overflow: assert property (
-        @(posedge clk_i) rst_ni && (commit_status_cnt_q == DEPTH_COMMIT) |-> !commit_i)
+        @(posedge clk_i) rst_ni && ({{$bits(DEPTH_COMMIT)-$bits(commit_status_cnt_q){1'b0}},commit_status_cnt_q} == DEPTH_COMMIT) |-> !commit_i)
         else $error("[Commit Queue] You are trying to commit a store although the buffer is full");
     //pragma translate_on
 endmodule

diff --git a/core/store_unit.sv b/core/store_unit.sv
@@ -185,7 +185,7 @@ module store_unit import ariane_pkg::*; #(
         st_be_n   = lsu_ctrl_i.be;
         // don't shift the data if we are going to perform an AMO as we still need to operate on this data
         st_data_n = instr_is_amo ? lsu_ctrl_i.data[riscv::XLEN-1:0]
-                                 : data_align(lsu_ctrl_i.vaddr[2:0], lsu_ctrl_i.data);
+                                 : data_align(lsu_ctrl_i.vaddr[2:0], {{64-$bits(lsu_ctrl_i.data){1'b0}},lsu_ctrl_i.data});
         st_data_size_n = extract_transfer_size(lsu_ctrl_i.operation);
         // save AMO op for next cycle
         case (lsu_ctrl_i.operation)