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drivers: intc: plic: implement riscv_plic_irq_set_pending() #78611

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merged 3 commits into from
Oct 9, 2024
Merged

drivers: intc: plic: implement riscv_plic_irq_set_pending() #78611

merged 3 commits into from
Oct 9, 2024

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ycsin
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@ycsin ycsin commented Sep 18, 2024 •
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Set an interrupt line as pending for PLIC that supports software-generated interrupt. Currently, this is only supported by Andes NCEPLIC100 ("andestech,nceplic100"), other PLICs can be supported by updating the Kconfig.

For more info, see #78611 (comment)

For context, this can be used for SMP IPI / mailbox

@ycsin ycsin marked this pull request as ready for review September 18, 2024 08:20
@zephyrbot zephyrbot added area: RISCV RISCV Architecture (32-bit & 64-bit) area: Interrupt Controller labels Sep 18, 2024
@ycsin ycsin requested a review from luchnikov September 18, 2024 14:07
cfriedt
cfriedt previously approved these changes Sep 18, 2024
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npitre
npitre previously approved these changes Sep 19, 2024
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@ycsin ycsin mentioned this pull request Sep 24, 2024
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jimmyzhe commented Sep 24, 2024 •
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Thank you for this PR, Andes platform works with this change. I plan to rework the mbox_andes_plic_sw driver after this PR is merged.

But I think not all PLIC implementation support software-triggered interrupt.
The RISC-V PLIC spec defines the Pending Bit can be read and cleared by the claim operation ,but it doesn't describe write operation. Some PLIC implementation mark Pend Bit as read-only.

擷取60

Andes PLIC describes it as an enhanced feature

擷取57

Maybe use #if IS_ENABLED(PLIC_DRV_HAS_COMPAT(andestech_nceplic100)) or add a Kconfig for PLICs that do not support this feature would be better.

@ycsin ycsin added the DNM This PR should not be merged (Do Not Merge) label Sep 24, 2024
@ycsin ycsin dismissed stale reviews from npitre and cfriedt via f9c0050 September 25, 2024 05:24
@ycsin ycsin force-pushed the pr/plic-irq-set-pending-minimal branch from c1ca2ac to f9c0050 Compare September 25, 2024 05:24
@ycsin ycsin requested a review from jimmyzhe as a code owner September 25, 2024 05:24
@ycsin ycsin removed the DNM This PR should not be merged (Do Not Merge) label Sep 25, 2024
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ycsin commented Sep 25, 2024 •
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@jimmyzhe thanks for pointing that out, that made a lot of sense to me. I've updated the patch accordingly to compile the feature only for NCEPLIC100 with Kconfig

I plan to rework the mbox_andes_plic_sw driver after this PR is merged.

Could you probably comment your plan in #78917, so that Andes mbox works alongside SMP? I can be reached with the same handle on Discord as well.

@ycsin ycsin force-pushed the pr/plic-irq-set-pending-minimal branch from f9c0050 to deee99b Compare September 25, 2024 05:47
jimmyzhe
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@ycsin ycsin requested review from npitre and cfriedt October 1, 2024 03:37
ycsin added 3 commits October 8, 2024 16:26
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dts: add andestech,nceplic100 binding
68c2708 
Add a new `andestech,nceplic100` binding that inherits from the
`sifive,plic-1.0.0` binding. This is so that the Kconfig
`DT_HAS_ANDESTECH_NCEPLIC100_ENABLED` would be generated during
build.

Signed-off-by: Yong Cong Sin <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin
drivers: intc: plic: implement software-generated interrupt
e7852e1 
Implement `riscv_plic_irq_set_pending()` to trigger a
software-generated interrupt.

The "4. Interrupt Pending Bits" of the riscv-plic specs
described the reading of the pending bits, but not the writing

Since not all PLIC implementations support software-generated
interrupt, the function is compiled only when
`CONFIG_PLIC_SUPPORTS_SOFT_INTERRUPT` is enabled on PLIC that
supports it, such as the Andes' NCEPLIC100.

Signed-off-by: Yong Cong Sin <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin
drivers: intc: plic: convert trigger type to use Kconfig
2d7c8d8 
Convert the compilation of the trigger type feature to depend
on Kconfig, following the same pattern of software-triggered
interrupt.

Signed-off-by: Yong Cong Sin <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin ycsin force-pushed the pr/plic-irq-set-pending-minimal branch from deee99b to 2d7c8d8 Compare October 8, 2024 08:34
@ycsin ycsin requested review from jimmyzhe and cfriedt October 8, 2024 08:34
@aescolar aescolar merged commit 9109cfe into zephyrproject-rtos:main Oct 9, 2024
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@ycsin ycsin deleted the pr/plic-irq-set-pending-minimal branch October 9, 2024 09:51
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ycsin commented Oct 9, 2024

🙌

@jimmyzhe jimmyzhe mentioned this pull request Oct 11, 2024
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