init: per-core init hook

arch/arc/core/smp.c

@@ -16,6 +16,7 @@
 #include <ipi.h>
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
+#include <zephyr/platform/hooks.h>
 #include <arc_irq_offload.h>
 
 volatile struct {
@@ -115,6 +116,11 @@ void arch_secondary_cpu_init(int cpu_num)
 			   DT_IRQ(DT_NODELABEL(ici), priority), 0);
 	irq_enable(DT_IRQN(DT_NODELABEL(ici)));
 #endif
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
+
 	/* call the function set by arch_cpu_start */
 	fn = arc_cpu_init[cpu_num].fn;
 

arch/arc/include/kernel_arch_func.h

@@ -26,13 +26,19 @@
 
 #include <v2/irq.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
 	z_irq_setup();
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 

arch/arm/core/cortex_a_r/smp.c

@@ -12,6 +12,7 @@
 #include "zephyr/cache.h"
 #include "zephyr/kernel/thread_stack.h"
 #include "zephyr/toolchain/gcc.h"
+#include <zephyr/platform/hooks.h>
 
 #define INV_MPID	UINT32_MAX
 
@@ -198,6 +199,10 @@ void arch_secondary_cpu_init(void)
 	 */
 #endif
 
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
+
 	fn = arm_cpu_boot_params.fn;
 	arg = arm_cpu_boot_params.arg;
 	barrier_dsync_fence_full();

arch/arm/include/cortex_a_r/kernel_arch_func.h

@@ -20,6 +20,8 @@
 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_
 #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_KERNEL_ARCH_FUNC_H_
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -28,6 +30,9 @@ extern "C" {
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 #ifndef CONFIG_USE_SWITCH

arch/arm/include/cortex_m/kernel_arch_func.h

@@ -20,6 +20,8 @@
 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_
 #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_KERNEL_ARCH_FUNC_H_
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -53,6 +55,10 @@ static ALWAYS_INLINE void arch_kernel_init(void)
 	 */
 	z_arm_configure_static_mpu_regions();
 #endif /* CONFIG_ARM_MPU */
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/arm64/core/smp.c

@@ -23,6 +23,7 @@
 #include <zephyr/drivers/interrupt_controller/gic.h>
 #include <zephyr/drivers/pm_cpu_ops.h>
 #include <zephyr/arch/arch_interface.h>
+#include <zephyr/platform/hooks.h>
 #include <zephyr/sys/barrier.h>
 #include <zephyr/irq.h>
 #include "boot.h"
@@ -163,6 +164,10 @@ void arch_secondary_cpu_init(int cpu_num)
 #endif
 #endif
 
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
+
 	fn = arm64_cpu_boot_params.fn;
 	arg = arm64_cpu_boot_params.arg;
 	barrier_dsync_fence_full();

arch/arm64/include/kernel_arch_func.h

@@ -22,6 +22,8 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -35,6 +37,10 @@ static ALWAYS_INLINE void arch_kernel_init(void)
 #ifdef CONFIG_XEN
 	xen_enlighten_init();
 #endif
+
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static inline void arch_switch(void *switch_to, void **switched_from)

arch/mips/include/kernel_arch_func.h

@@ -19,13 +19,18 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/nios2/include/kernel_arch_func.h

@@ -22,6 +22,8 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -30,6 +32,9 @@ extern "C" {
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/posix/include/kernel_arch_func.h

@@ -12,6 +12,8 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifndef _ASMLANGUAGE
 
 #ifdef __cplusplus
@@ -20,7 +22,9 @@ extern "C" {
 
 static inline void arch_kernel_init(void)
 {
-	/* Nothing to be done */
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/riscv/core/smp.c

@@ -12,6 +12,7 @@
 #include <zephyr/sys/atomic.h>
 #include <zephyr/arch/riscv/irq.h>
 #include <zephyr/drivers/pm_cpu_ops.h>
+#include <zephyr/platform/hooks.h>
 
 volatile struct {
 	arch_cpustart_t fn;
@@ -79,6 +80,9 @@ void arch_secondary_cpu_init(int hartid)
 	/* Enable on secondary cores so that they can respond to PLIC */
 	irq_enable(RISCV_IRQ_MEXT);
 #endif /* CONFIG_PLIC_IRQ_AFFINITY */
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 	riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg);
 }
 

arch/riscv/include/kernel_arch_func.h

@@ -18,6 +18,8 @@
 #include <kernel_arch_data.h>
 #include <pmp.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -53,6 +55,9 @@ static ALWAYS_INLINE void arch_kernel_init(void)
 #ifdef CONFIG_RISCV_PMP
 	z_riscv_pmp_init();
 #endif
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/sparc/include/kernel_arch_func.h

@@ -17,13 +17,18 @@
 
 #include <kernel_arch_data.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #ifndef _ASMLANGUAGE
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 void z_sparc_context_switch(struct k_thread *newt, struct k_thread *oldt);

arch/x86/include/ia32/kernel_arch_func.h

@@ -14,13 +14,17 @@
 
 #include <stddef.h> /* For size_t */
 
+#include <zephyr/platform/hooks.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 static inline void arch_kernel_init(void)
 {
-	/* No-op on this arch */
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 static ALWAYS_INLINE void

arch/x86/include/intel64/kernel_arch_func.h

@@ -8,6 +8,8 @@
 
 #include <zephyr/kernel_structs.h>
 
+#include <zephyr/platform/hooks.h>
+
 #ifndef _ASMLANGUAGE
 
 extern void z_x86_switch(void *switch_to, void **switched_from);
@@ -27,7 +29,9 @@ extern void z_x86_ipi_setup(void);
 
 static inline void arch_kernel_init(void)
 {
-	/* nothing */;
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot);

arch/xtensa/include/kernel_arch_func.h

@@ -14,6 +14,7 @@
 #include <kernel_internal.h>
 #include <string.h>
 #include <zephyr/cache.h>
+#include <zephyr/platform/hooks.h>
 #include <zephyr/zsr.h>
 
 #ifdef __cplusplus
@@ -25,7 +26,9 @@ K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS,
 
 static ALWAYS_INLINE void arch_kernel_init(void)
 {
-
+#ifdef CONFIG_SOC_PER_CORE_INIT_HOOK
+	soc_per_core_init_hook();
+#endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
 void xtensa_switch(void *switch_to, void **switched_from);

include/zephyr/platform/hooks.h

@@ -53,6 +53,14 @@ void soc_early_init_hook(void);
  */
 void soc_late_init_hook(void);
 
+/**
+ * @brief SoC per-core initialization
+ *
+ * This hook is implemented by the SoC and can be used to perform any
+ * SoC-specific per-core initialization
+ */
+void soc_per_core_init_hook(void);
+
 /*
  * @brief Board hook executed before the kernel starts.
  *

kernel/Kconfig.init

@@ -38,6 +38,15 @@ config SOC_LATE_INIT_HOOK
 	  A custom SoC hook soc_late_init_hook() is executed after the kernel and
 	  devices are initialized
 
+config SOC_PER_CORE_INIT_HOOK
+	bool "Run SoC per-core initialization hook"
+	help
+	  Run an SoC initialization hook for every core
+
+	  A custom SoC hook soc_per_core_init_hook() is executeds at the end of
+	  arch_kernel_init() for the primary core, and at the end of arch_secondary_cpu_init()
+	  for secondary cores.
+
 config BOARD_EARLY_INIT_HOOK
 	bool "Run early board hook"
 	help

soc/andestech/ae350/CMakeLists.txt

@@ -3,6 +3,7 @@
 zephyr_include_directories(.)
 
 zephyr_sources(
+  soc.c
   start.S
   soc_irq.S
 )

soc/andestech/ae350/Kconfig

@@ -92,6 +92,7 @@ config SOC_ANDES_V5_PMA
 	bool "Andes V5 Physical Memory Attribute (PMA)"
 	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 	select SOC_EARLY_INIT_HOOK
+	select SOC_PER_CORE_INIT_HOOK
 	help
 		This option enables the Andes V5 PMA, in order to support SW to
 		configure physical memory attribute by PMA CSRs. The address

soc/andestech/ae350/pma.c

@@ -187,21 +187,14 @@ static void configure_nocache_region(void)
 }
 #endif /* CONFIG_NOCACHE_MEMORY */
 
-/*
- * @brief Init PMA CSRs of each CPU core
- *
- * In SMP, each CPU has it's own PMA CSR and PMA CSR only affect one CPU.
- * We should configure CSRs of all CPUs to make memory attribute
- * (e.g. uncacheable) affects all CPUs.
- */
 void pma_init_per_core(void)
 {
 #ifdef CONFIG_NOCACHE_MEMORY
 	configure_nocache_region();
 #endif /* CONFIG_NOCACHE_MEMORY */
 }
 
-void soc_early_init_hook(void)
+void pma_init(void)
 {
 	unsigned long mmsc_cfg;
 
@@ -216,8 +209,6 @@ void soc_early_init_hook(void)
 		LOG_ERR("CPU doesn't support PMA. "
 			"Please disable CONFIG_SOC_ANDES_V5_PMA");
 #endif
-		return -ENODEV;
+		return;
 	}
-
-	pma_init_per_core();
 }