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drivers: intc: plic: add support for multiple instances #62907

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merged 5 commits into from
Nov 9, 2023
Merged

drivers: intc: plic: add support for multiple instances #62907

merged 5 commits into from
Nov 9, 2023

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ycsin
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@ycsin ycsin commented Sep 21, 2023 •
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  1. Refactored the build_all test added in drivers: intc: plic: fix the calculation of trig register #62541
  2. Refactored the intc_plic driver to be multi-instance ready
  3. Updated the sw_isr_* so that it also records the device pointer of the interrupt controllers & provide functions to do a lookup for the controller using the IRQN, as well as getting the ISR table offset for a controller
  4. Updated the intc_plic driver to use the functions in the sw_isr so that it can differentiate parent controller from IRQN, and invoke the correct ISR with the correct offset from sw_isr_*
    • Modified some description in the riscv_plic header file, previously the driver expects the trimmed IRQN returned by irq_from_level_2 as there can only be one controller, with multi-instance, we need the full multi-level-encoded IRQN, so that the driver can determine the right controller with z_get_sw_isr_device using the 1st level IRQ.
  5. Added a build_all test for multi-instance on qemu_riscv* as no QEMU machine supports more than one PLIC. Not sure if this is helpful.

fixes #62441
fixes #62956
fixes #63465

@ycsin ycsin added area: RISCV RISCV Architecture (32-bit & 64-bit) area: Interrupt Controller labels Sep 21, 2023
@ycsin ycsin changed the title [drivers][interrupt-controller][plic] Add support for multiple instances [drivers][interrupt-controller][riscv-plic] Add support for multiple instances Sep 21, 2023
@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch from 63fcbe4 to bfc4bda Compare September 21, 2023 10:01
@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch 9 times, most recently from 40a87a0 to b5589f3 Compare September 25, 2023 05:59
@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch from b5589f3 to 772d36a Compare September 25, 2023 07:51
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ycsin commented Sep 25, 2023 •
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The am62x_m4_* fails to build when zephyr/device.h is included in sw_isr_table.h, see #63036
merged

@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch from 9324eb4 to 2d6b199 Compare September 26, 2023 06:43
@ycsin ycsin marked this pull request as ready for review September 26, 2023 08:29
@ycsin ycsin changed the title [drivers][interrupt-controller][riscv-plic] Add support for multiple instances drivers: intc: plic: add support for multiple instances Oct 3, 2023
cfriedt
cfriedt previously approved these changes Oct 3, 2023
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Pre-emptively acking. Please remember to rebase once #63172 is merged (for sw_isr_common changes)

@fabiobaltieri fabiobaltieri added this to the v3.5.0 milestone Oct 3, 2023
@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch from 21e8387 to 6548d76 Compare October 4, 2023 14:33
ycsin
ycsin commented Oct 4, 2023
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arch/common/sw_isr_common.c Outdated Show resolved Hide resolved
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Pre-emptively acking. Please remember to rebase once #63172 is merged (for sw_isr_common changes)

#63172 wasn't flagged for 3.5 even though this PR is. I fixed the milestone for the other PR, but it's getting quite late in the game for 3.5 to introduce such big changes.

cfriedt
cfriedt previously approved these changes Oct 11, 2023
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@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch from 6548d76 to 2b6e000 Compare October 16, 2023 08:07
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ycsin commented Oct 16, 2023

rebased on top of #63172, following the changes over there

cfriedt
cfriedt previously approved these changes Oct 16, 2023
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@fabiobaltieri fabiobaltieri removed this from the v3.5.0 milestone Oct 17, 2023
@ycsin ycsin mentioned this pull request Oct 25, 2023
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ycsin added 2 commits November 9, 2023 18:37
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drivers: intc: plic: initial refactor for multi-instance support
2fb6ac3 
Use a config struct to store per-instance device config during
init and connect the IRQ based on the devicetree instead of
hardcoded value and instance number.

The `get_plic_dev_from_irq` is still a placeholder for now and
always return the first instance.

Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin
drivers: plic: support multiple instances for multi-level
dce9c22 
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.

Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch from 2b6e000 to 747467e Compare November 9, 2023 10:39
@ycsin ycsin removed the DNM This PR should not be merged (Do Not Merge) label Nov 9, 2023
@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch 2 times, most recently from 0f61111 to 6b4f996 Compare November 9, 2023 10:48
ycsin added 3 commits November 9, 2023 18:54
@ycsin
tests: build_all: plic: multi instance
8dfabec 
Add PLIC multi-instance build-only test.

Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin
drivers: intc: plic: make sense of magic number
e128fbd 
Added some defines and helper functions to help with the
arithmetics so that the bit shifts and stuff do not look like
magic number.

Converted manual bit shift/set/unset to use macros provided by
Zephyr.

Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin
drivers: intc: plic: Use sys IO APIs to access memory-mapped registers
ec0ae61 
Use arch-specific sys IO APIs to access the memory-mapped
registers to ensure safe memory operations

fixes zephyrproject-rtos#62956

Signed-off-by: Yong Cong Sin <[email protected]>
@ycsin ycsin force-pushed the pr/plic_multi_instance_2 branch from 6b4f996 to ec0ae61 Compare November 9, 2023 10:55
@carlescufi carlescufi merged commit ffb8f31 into zephyrproject-rtos:main Nov 9, 2023
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@ycsin ycsin deleted the pr/plic_multi_instance_2 branch July 15, 2024 05:40
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area: Architectures area: Devicetree Binding PR modifies or adds a Device Tree binding area: Interrupt Controller area: Kernel area: RISCV RISCV Architecture (32-bit & 64-bit)
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