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Add acpi device resource enumeration support #62694

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merged 12 commits into from
Jan 31, 2024
Merged

Add acpi device resource enumeration support #62694

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951ae52
arch: x86: add a sperate timer interface for acpica lib
najumon1980 Nov 9, 2023
8ecbe96
manifest: update west point to latest acpica commit
najumon1980 Nov 9, 2023
ec96619
arch: x86: add interface for encode irq flags
najumon1980 Sep 15, 2023
a5e52de
lib: acpi: add device resource enum support
najumon1980 Sep 15, 2023
f73a6a9
boards: x86: add pci controller node with acpi pnp id
najumon1980 Oct 31, 2023
122af4c
drivers: pci: update prt retrieve based on pnp id
najumon1980 Oct 31, 2023
eb83021
lib: acpi: add resource enumeration shell command
najumon1980 Sep 23, 2023
1a3fbd5
dts: rtc: mc146818: add acpi hid support in yaml file
najumon1980 Dec 1, 2023
0cbbdb0
tests: remove pci bus compatible id dependency from overlay files
najumon1980 Nov 17, 2023
c58b8e4
tests: lib: acpi: update test cases for dev and resource enum
najumon1980 Nov 10, 2023
142cfaf
docs: rename intel,pcie compatible id to pcie-controller
najumon1980 Nov 17, 2023
08ecb14
tests: lib: acpi: add fake x86 acpi function
najumon1980 Jan 22, 2024
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1 change: 1 addition & 0 deletions arch/x86/core/CMakeLists.txt
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Expand Up @@ -16,6 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_REBOOT_RST_CNT reboot_rst_cnt.c)
zephyr_library_sources_ifdef(CONFIG_MULTIBOOT_INFO multiboot.c)
zephyr_library_sources_ifdef(CONFIG_X86_EFI efi.c)
zephyr_library_sources_ifdef(CONFIG_ACPI legacy_bios.c)
zephyr_library_sources_ifdef(CONFIG_ACPI x86_acpi.c)
zephyr_library_sources_ifdef(CONFIG_X86_MMU x86_mmu.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.c)
zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)
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26 changes: 26 additions & 0 deletions arch/x86/core/x86_acpi.c
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@@ -0,0 +1,26 @@
/*
* Copyright (c) 2023, Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/acpi/acpi.h>
#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>

uint32_t arch_acpi_encode_irq_flags(uint8_t polarity, uint8_t trigger)
{
uint32_t irq_flag = IRQ_DELIVERY_LOWEST;

if (trigger == ACPI_LEVEL_SENSITIVE) {
irq_flag |= IRQ_TYPE_LEVEL;
} else {
irq_flag |= IRQ_TYPE_EDGE;
}

if (polarity == ACPI_ACTIVE_HIGH) {
irq_flag |= IRQ_TYPE_HIGH;
} else if (polarity == ACPI_ACTIVE_LOW) {
irq_flag |= IRQ_TYPE_LOW;
}

return irq_flag;
}
2 changes: 0 additions & 2 deletions boards/x86/intel_adl/Kconfig.defconfig
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Expand Up @@ -37,8 +37,6 @@ config HEAP_MEM_POOL_ADD_SIZE_ACPI
default 64000000
config MAIN_STACK_SIZE
default 320000
config ACPI_PRT_BUS_NAME
default "_SB.PC00"

if SHELL
config SHELL_STACK_SIZE
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4 changes: 0 additions & 4 deletions boards/x86/intel_ehl/Kconfig.defconfig
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Expand Up @@ -19,10 +19,6 @@ config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN
default n
endif

config ACPI_PRT_BUS_NAME
depends on ACPI
default "_SB.PC00"

config HEAP_MEM_POOL_ADD_SIZE_ACPI
default 2097152
depends on ACPI
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2 changes: 0 additions & 2 deletions boards/x86/intel_rpl/Kconfig.defconfig
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Expand Up @@ -36,8 +36,6 @@ config HEAP_MEM_POOL_ADD_SIZE_ACPI
default 64000000
config MAIN_STACK_SIZE
default 320000
config ACPI_PRT_BUS_NAME
default "_SB.PC00"

if SHELL
config SHELL_STACK_SIZE
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3 changes: 2 additions & 1 deletion boards/x86/qemu_x86/qemu_x86.dts
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Expand Up @@ -49,7 +49,8 @@
pcie0: pcie0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
compatible = "pcie-controller";
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so this change should go in the previous patch that remove "intel,pcie"

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Which commit you referring ? This commit is specifically for board configuration changes

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Which commit you referring ? This commit is specifically for board configuration changes

I think @tbursztyka is referring to the commit where you remove the intel,pcie binding (yaml) file. Once that file is removed there shouldn't be any more references to "intel,pcie" in dts files or the documentation.

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Which commit you referring ? This commit is specifically for board configuration changes

I think @tbursztyka is referring to the commit where you remove the intel,pcie binding (yaml) file. Once that file is removed there shouldn't be any more references to "intel,pcie" in dts files or the documentation.

updated

acpi-hid = "PNP0A08";
ranges;

can0: can0 {
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5 changes: 0 additions & 5 deletions doc/services/storage/disk/nvme.rst
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Expand Up @@ -43,11 +43,6 @@ Any board exposing an NVMe disk should provide a DTS overlay to enable its use w
#include <zephyr/dt-bindings/pcie/pcie.h>
/ {
pcie0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
ranges;

nvme0: nvme0 {
compatible = "nvme-controller";
vendor-id = <VENDOR_ID>;
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32 changes: 31 additions & 1 deletion drivers/pcie/host/pcie.c
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Expand Up @@ -5,6 +5,8 @@
* SPDX-License-Identifier: Apache-2.0
*/

#define DT_DRV_COMPAT pcie_controller

#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pcie, LOG_LEVEL_ERR);

Expand All @@ -28,6 +30,11 @@ LOG_MODULE_REGISTER(pcie, LOG_LEVEL_ERR);
#include <zephyr/drivers/pcie/controller.h>
#endif

#ifdef CONFIG_PCIE_PRT
/* platform interrupt are hardwired or can be dynamically allocated. */
static bool prt_en;
#endif

/* functions documented in drivers/pcie/pcie.h */

bool pcie_probe(pcie_bdf_t bdf, pcie_id_t id)
Expand Down Expand Up @@ -303,8 +310,16 @@ unsigned int pcie_alloc_irq(pcie_bdf_t bdf)
irq >= CONFIG_MAX_IRQ_LINES ||
arch_irq_is_used(irq)) {

/* In some platforms, PCI interrupts are hardwired to specific interrupt inputs
* on the interrupt controller and are not configurable. Hence we need to retrieve
* IRQ from acpi. But if it is configurable then we allocate irq dynamically.
*/
#ifdef CONFIG_PCIE_PRT
irq = acpi_legacy_irq_get(bdf);
if (prt_en) {
irq = acpi_legacy_irq_get(bdf);
} else {
irq = arch_irq_allocate();
}
#else
irq = arch_irq_allocate();
#endif
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rewrite the above so it becomes:

#ifdef CONFIG_PCIE_PRT
		irq = acpi_legacy_irq_get(bdf);
		if (prt_base_irq) {
			irq = acpi_legacy_irq_get(bdf);
		} else
#else
                {
			irq = arch_irq_allocate();
		}
#endif

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@jhedberg jhedberg Dec 21, 2023 •
edited
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rewrite the above so it becomes:

@tbursztyka I don't think what you proposed will generate correct code, since it leaves out the arch_irq_allocate() call completely if CONFIG_PCIE_PRT is set. Anyway, think Najumon's original code is actually a bit more readable, even though there's arch_irq_allocate() in two places.

Expand Down Expand Up @@ -545,6 +560,21 @@ static int pcie_init(void)
.flags = PCIE_SCAN_RECURSIVE,
};

#ifdef CONFIG_PCIE_PRT
const char *hid, *uid = ACPI_DT_UID(DT_DRV_INST(0));
int ret;

BUILD_ASSERT(ACPI_DT_HAS_HID(DT_DRV_INST(0)),
"No HID property for PCIe devicetree node");
hid = ACPI_DT_HID(DT_DRV_INST(0));

ret = acpi_legacy_irq_init(hid, uid);
if (!ret) {
prt_en = true;
} else {
__ASSERT(ret == -ENOENT, "Error retrieve interrupt routing table!");
}
#endif

STRUCT_SECTION_COUNT(pcie_dev, &data.max_dev);
/* Don't bother calling pcie_scan() if there are no devices to look for */
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23 changes: 23 additions & 0 deletions dts/bindings/acpi/acpi.yaml
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@@ -0,0 +1,23 @@
# Copyright (c) 2023 Intel Corporation
# SPDX-License-Identifier: Apache-2.0

# Common fields for ACPI informed based devices

properties:
acpi-hid:
type: string
description: Used to supply OSPM with the device’s PNP ID or ACPI ID.
A node is consder as acpi based or not based on whether this property
is present or not.

acpi-uid:
type: string
description: |
Provides OSPM with a logical device ID that does not change
across reboots. This object is optional, but is required when the device
has no other way to report a persistent unique device ID. The _UID must be
unique across all devices with either a common _HID or _CID.

acpi-comp-id:
type: string-array
description: Used to supply OSPM with a device’s Plug and Play-Compatible Device ID
8 changes: 0 additions & 8 deletions dts/bindings/pcie/host/intel,pcie.yaml
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This file was deleted.

6 changes: 5 additions & 1 deletion dts/bindings/pcie/host/pcie-controller.yaml
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Expand Up @@ -3,7 +3,11 @@

# Common fields for PCIe bus controllers

include: base.yaml
include: [base.yaml, acpi.yaml]

description: Generic PCIe host controller

compatible: "pcie-controller"

bus: pcie

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2 changes: 1 addition & 1 deletion dts/bindings/rtc/motorola,mc146818.yaml
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Expand Up @@ -6,7 +6,7 @@ description: Motorola MC146818 compatible Real Timer Clock

compatible: "motorola,mc146818"

include: rtc-device.yaml
include: [rtc-device.yaml, acpi.yaml]

properties:
clock-frequency:
Expand Down
3 changes: 2 additions & 1 deletion dts/x86/intel/alder_lake.dtsi
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Expand Up @@ -48,7 +48,8 @@
pcie0: pcie0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
compatible = "pcie-controller";
acpi-hid = "PNP0A08";
ranges;

smbus0: smbus0 {
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3 changes: 2 additions & 1 deletion dts/x86/intel/apollo_lake.dtsi
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Expand Up @@ -47,7 +47,8 @@
pcie0: pcie0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
compatible = "pcie-controller";
acpi-hid = "PNP0A08";
ranges;

uart0: uart0 {
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3 changes: 2 additions & 1 deletion dts/x86/intel/elkhart_lake.dtsi
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Expand Up @@ -52,7 +52,8 @@
pcie0: pcie0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
compatible = "pcie-controller";
acpi-hid = "PNP0A08";
ranges;

ptm_root0: ptm_root0 {
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3 changes: 2 additions & 1 deletion dts/x86/intel/raptor_lake_p.dtsi
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Expand Up @@ -43,9 +43,10 @@
};

pcie0: pcie0 {
compatible = "intel,pcie";
compatible = "pcie-controller";
#address-cells = <1>;
#size-cells = <1>;
acpi-hid = "PNP0A08";
ranges;

smbus0: smbus0 {
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3 changes: 2 additions & 1 deletion dts/x86/intel/raptor_lake_s.dtsi
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Expand Up @@ -47,7 +47,8 @@
pcie0: pcie0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,pcie";
compatible = "pcie-controller";
acpi-hid = "PNP0A08";
ranges;

smbus0: smbus0 {
Expand Down
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