Add support for Cortex-A/R AArch32 cache management APIs #56178
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manuargue
requested review from
stephanosio,
MaureenHelm,
galak,
ioannisg and
bbolen
as code owners
|
unrelated twister build failures for |
This was referenced Mar 24, 2023
carlocaione
previously approved these changes
Mar 27, 2023
|
@manuargue Seeing some CI failures, though only one related to Arm. |
yes, logged this in #56188 and #56189, but both are failing in main. The first is being addressed already, for the second I may have time today to look at it (if not fixed already). |
microbuilder
previously approved these changes
Mar 27, 2023
Current implementation of cache management APIs for ARM only applies to Cortex-M, so move it to its own directory. Signed-off-by: Manuel Argüelles <[email protected]>
Implement cache management APIs for Cortex-A/R AArch32 L1 caches. Signed-off-by: Manuel Argüelles <[email protected]>
When CONFIG_NOCACHE_MEMORY=y, the .nocache section is placed in between __rodata_region_end and _app_smem_start/__kernel_ram_start. Make sure this region is covered by the MPU background region so that the static region for nocache is configured correctly. Signed-off-by: Manuel Argüelles <[email protected]>
Enable at SoC boot time when enabled through Kconfig. Cache management API is not used since it could be built without its support enabled. Signed-off-by: Manuel Argüelles <[email protected]>
Build with cache management enabled by default on this board. Signed-off-by: Manuel Argüelles <[email protected]>
manuargue
dismissed stale reviews from microbuilder and carlocaione
via
a415045
|
rebased to pickup fixes from |
microbuilder
approved these changes
Mar 28, 2023
povergoing
approved these changes
Mar 29, 2023
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Add support for Cortex-A/R AArch32 (L1) cache management APIs through CMSIS. Cortex-M cache implementation is moved to its own directory as it's not generic for all Arm architectures.
Also enabled caches on
fvp_baser_aemv8r_aarch32to have a Cortex-R AArch32 FVP board with caches enabled.