arch: riscv: Add support for custom IPI implementation

Allow RISCV implementation to define its own custom IPI implementation (e.g. Andes usage of PLIC for IPI) Signed-off-by: Maxim Adelman <[email protected]
zephyrproject-rtos · Nov 27, 2023 · d82ffcb · d82ffcb
1 parent a43e516
commit d82ffcb
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diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
@@ -100,6 +100,13 @@ config RISCV_SOC_HAS_CUSTOM_SYS_IO
 	  the RISC-V SoC needs to do something different and more than reading and
 	  writing the registers.
 
+config RISCV_SOC_HAS_CUSTOM_SMP_IPI
+	bool
+	select SCHED_IPI_SUPPORTED
+	help
+	  Hidden option to allow SoC to overwrite SMP IPI implementation
+	  Enable this hidden option and implement arch_sched_ipi()
+
 config RISCV_SOC_CONTEXT_SAVE
 	bool "SOC-based context saving in IRQ handlers"
 	select RISCV_SOC_OFFSETS

diff --git a/arch/riscv/core/smp.c b/arch/riscv/core/smp.c
@@ -72,7 +72,8 @@ void z_riscv_secondary_cpu_init(int hartid)
 	riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg);
 }
 
-#ifdef CONFIG_SMP
+/* IPI */
+#if defined(CONFIG_SMP) && !defined(CONFIG_RISCV_SOC_HAS_CUSTOM_SMP_IPI)
 
 #define MSIP(hartid) ((volatile uint32_t *)RISCV_MSIP_BASE)[hartid]