soc: renode: cortex_r8_virtual: overhaul MPU regions

Apply the same modifications made to the ZynqMP's memory
regions to the cortex_r8_virtual SoC which was mainlined
while the fixes for the ZynqMP were being developed
(minus the OCM mapping, as there's no indication that this
type of memory was considered).

The cortex_r8_virtual appears to be a stripped down copy
of the old qemu_cortex_r5 codebase, therefore, the duplicated
MPU regions have the same flaws as qemu_cortex_r5 or any
actual ZynqMP-based target for that matter.

Signed-off-by: Immo Birnbaum <[email protected]>

soc/renode/cortex_r8_virtual/arm_mpu_regions.c

@@ -2,62 +2,67 @@
  *
  * Copyright (c) 2021 Lexmark International, Inc.
  * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ * Copyright (c) 2024 Immo Birnbaum
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/mpu/arm_mpu.h>
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
 
-#define MPUTYPE_READ_ONLY \
-	{ \
-		.rasr = (P_RO_U_RO_Msk \
-				| (7 << MPU_RASR_TEX_Pos) \
-				| MPU_RASR_C_Msk \
-				| MPU_RASR_B_Msk \
-				| MPU_RASR_XN_Msk) \
-	}
+extern const uint32_t __rom_region_start;
+extern const uint32_t __rom_region_mpu_size_bits;
 
-#define MPUTYPE_READ_ONLY_PRIV \
-	{ \
-		.rasr = (P_RO_U_RO_Msk \
-				| (5 << MPU_RASR_TEX_Pos) \
-				| MPU_RASR_B_Msk) \
-	}
-
-#define MPUTYPE_PRIV_WBWACACHE_XN \
-	{ \
-		.rasr = (P_RW_U_NA_Msk \
-				| (5 << MPU_RASR_TEX_Pos) \
-				| MPU_RASR_B_Msk \
-				| MPU_RASR_XN_Msk) \
-	}
-
-#define MPUTYPE_PRIV_DEVICE \
-	{ \
-		.rasr = (P_RW_U_NA_Msk \
-				| (2 << MPU_RASR_TEX_Pos)) \
-	}
-
-extern uint32_t _image_rom_end_order;
 static const struct arm_mpu_region mpu_regions[] = {
-	MPU_REGION_ENTRY("FLASH0",
-			0xc0000000,
-			REGION_32M,
-			MPUTYPE_READ_ONLY),
-
-	MPU_REGION_ENTRY("SRAM_PRIV",
-			0x00000000,
-			REGION_2G,
-			MPUTYPE_PRIV_WBWACACHE_XN),
-
-	MPU_REGION_ENTRY("SRAM",
-			0x00000000,
-			((uint32_t)&_image_rom_end_order),
-			MPUTYPE_READ_ONLY_PRIV),
-
-	MPU_REGION_ENTRY("REGISTERS",
-			0xf8000000,
-			REGION_128M,
-			MPUTYPE_PRIV_DEVICE),
+	/*
+	 * The address of the vectors is determined by arch/arm/core/cortex_a_r/prep_c.c
+	 * -> for v8-R, there's no other option than 0x0, HIVECS always gets cleared
+	 */
+	MPU_REGION_ENTRY(
+		"vectors",
+		0x00000000,
+		REGION_64B,
+		{.rasr = P_RO_U_NA_Msk |
+			 NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}),
+	/* Basic SRAM mapping is all data, R/W + XN */
+	MPU_REGION_ENTRY(
+		"sram",
+		CONFIG_SRAM_BASE_ADDRESS,
+		REGION_SRAM_SIZE,
+		{.rasr = P_RW_U_NA_Msk |
+			 NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE |
+			 NOT_EXEC}),
+#if defined(CONFIG_XIP)
+	/* .text and .rodata (=rom_region) are in flash, must be RO + executable */
+	MPU_REGION_ENTRY(
+		"rom_region",
+		CONFIG_FLASH_BASE_ADDRESS,
+		REGION_FLASH_SIZE,
+		{.rasr = P_RO_U_RO_Msk |
+			 NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}),
+	/* RAM contains R/W data, non-executable */
+#else /* !CONFIG_XIP */
+	/* .text and .rodata are in RAM, flash is data only -> RO + XN */
+	MPU_REGION_ENTRY(
+		"flash",
+		CONFIG_FLASH_BASE_ADDRESS,
+		REGION_FLASH_SIZE,
+		{.rasr = P_RO_U_RO_Msk |
+			 NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE |
+			 NOT_EXEC}),
+	/* add rom_region mapping for SRAM which is RO + executable */
+	MPU_REGION_ENTRY(
+		"rom_region",
+		(uint32_t)(&__rom_region_start),
+		(uint32_t)(&__rom_region_mpu_size_bits),
+		{.rasr = P_RO_U_RO_Msk |
+			 NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}),
+#endif /* CONFIG_XIP */
+	MPU_REGION_ENTRY(
+		"peripherals",
+		0xf8000000,
+		REGION_128M,
+		{.rasr = P_RW_U_NA_Msk |
+			 DEVICE_SHAREABLE |
+			 NOT_EXEC}),
 };
 
 const struct arm_mpu_config mpu_config = {