Skip to content

Commit

Permalink
drivers: clock control: stm32 function to get 48MHz freq
Browse files Browse the repository at this point in the history
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source

Signed-off-by: Francois Ramu <[email protected]>
  • Loading branch information
FRASTM committed Nov 29, 2024
1 parent 35f59c4 commit 7ffa15a
Show file tree
Hide file tree
Showing 3 changed files with 35 additions and 1 deletion.
2 changes: 1 addition & 1 deletion drivers/clock_control/clock_stm32_ll_common.c
Original file line number Diff line number Diff line change
Expand Up @@ -484,7 +484,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
#endif /* STM32_HSI48_ENABLED */
#if defined(STM32_CK48_ENABLED)
case STM32_SRC_CK48:
*rate = STM32_CK48_FREQ;
*rate = get_ck48_frequency();
break;
#endif /* STM32_CK48_ENABLED */

Expand Down
4 changes: 4 additions & 0 deletions drivers/clock_control/clock_stm32_ll_common.h
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,10 @@ void config_enable_default_clocks(void);
void config_regulator_voltage(uint32_t hclk_freq);
int enabled_clock(uint32_t src_clk);

#if defined(STM32_CK48_ENABLED)
uint32_t get_ck48_frequency(void);
#endif

/* functions exported to the soc power.c */
int stm32_clock_control_init(const struct device *dev);
void stm32_clock_control_standby_exit(void);
Expand Down
30 changes: 30 additions & 0 deletions drivers/clock_control/clock_stm32f2_f4_f7.c
Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,36 @@ uint32_t get_pllsrc_frequency(void)
return 0;
}

#if defined(STM32_CK48_ENABLED)
/**
* @brief calculate the CK48 frequency depending on its clock source
*/
__unused
uint32_t get_ck48_frequency(void)
{
if (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE) ==
LL_RCC_CK48M_CLKSOURCE_PLL) {
/* Get the PLL Q freq. No HAL macro for that */
return __LL_RCC_CALC_PLLCLK_48M_FREQ(HSE_VALUE,
LL_RCC_PLLI2S_GetDivider(),
LL_RCC_PLLI2S_GetN(),
LL_RCC_PLLI2S_GetQ()
);
} else if (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE) ==
LL_RCC_CK48M_CLKSOURCE_PLLI2S) {
/* Get the I2S PLL Q freq. No HAL macro for that */
return __LL_RCC_CALC_PLLI2S_48M_FREQ(HSE_VALUE,
LL_RCC_PLLI2S_GetDivider(),
LL_RCC_PLLI2S_GetN(),
LL_RCC_PLLI2S_GetQ()
);
}

__ASSERT(0, "Invalid source");
return 0;
}
#endif

/**
* @brief Set up pll configuration
*/
Expand Down

0 comments on commit 7ffa15a

Please sign in to comment.