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soc: xlnx: zynqmp: overhaul the Cortex-R MPU setup #156927

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soc: xlnx: zynqmp: overhaul the Cortex-R MPU setup

soc: xlnx: zynqmp: overhaul the Cortex-R MPU setup #156927

Triggered via pull request October 23, 2024 19:03
@ibirnbaumibirnbaum
synchronize #79221
ibirnbaum:zyqnmp_rpu_mpu
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compliance.yml

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Run compliance checks on patch series (PR): ClangFormat.txt#L1
See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details. You may want to run clang-format on this change: - MPU_REGION_ENTRY( - "vectors", - 0x00000000, - REGION_64B, - {.rasr = P_RO_U_NA_Msk | - NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + MPU_REGION_ENTRY("vectors", 0x00000000, REGION_64B, + {.rasr = P_RO_U_NA_Msk | NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), /* Basic SRAM mapping is all data, R/W + XN */ - MPU_REGION_ENTRY( - "sram", - CONFIG_SRAM_BASE_ADDRESS, - REGION_SRAM_SIZE, - {.rasr = P_RW_U_NA_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("sram", CONFIG_SRAM_BASE_ADDRESS, REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), #if defined(CONFIG_XIP) /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ - MPU_REGION_ENTRY( - "rom_region", - CONFIG_FLASH_BASE_ADDRESS, - REGION_FLASH_SIZE, - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), - /* RAM contains R/W data, non-executable */ -#else /* !CONFIG_XIP */ + MPU_REGION_ENTRY("rom_region", CONFIG_FLASH_BASE_ADDRESS, REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), +/* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ /* .text and .rodata are in RAM, flash is data only -> RO + XN */ MPU_REGION_ENTRY( - "flash", - CONFIG_FLASH_BASE_ADDRESS, - REGION_FLASH_SIZE, - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | - NOT_EXEC}), + "flash", CONFIG_FLASH_BASE_ADDRESS, REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | NOT_EXEC}), /* add rom_region mapping for SRAM which is RO + executable */ - MPU_REGION_ENTRY( - "rom_region", - (uint32_t)(&__rom_region_start), - (uint32_t)(&__rom_region_mpu_size_bits), - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), + MPU_REGION_ENTRY("rom_region", (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), #endif /* CONFIG_XIP */ - MPU_REGION_ENTRY( - "peripherals", - 0xf8000000, - REGION_128M, - {.rasr = P_RW_U_NA_Msk | - DEVICE_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("peripherals", 0xf8000000, REGION_128M, + {.rasr = P_RW_U_NA_Msk | DEVICE_SHAREABLE | NOT_EXEC}), File:soc/renode/cortex_r8_virtual/arm_mpu_regions.c Line:66 You may want to run clang-format on this change: - MPU_REGION_ENTRY( - "vectors", - 0x00000000, - REGION_64B, - {.rasr = P_RO_U_NA_Msk | - NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + MPU_REGION_ENTRY("vectors", 0x00000000, REGION_64B, + {.rasr = P_RO_U_NA_Msk | NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), /* Basic SRAM mapping is all data, R/W + XN */ - MPU_REGION_ENTRY( - "sram", - CONFIG_SRAM_BASE_ADDRESS, - REGION_SRAM_SIZE, - {.rasr = P_RW_U_NA_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("sram", CONFIG_SRAM_BASE_ADDRESS, REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), #if defined(CONFIG_XIP) /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ - MPU_REGION_ENTRY( - "rom_region", - CONFIG_FLASH_BASE_ADDRESS, - REGION_FLASH_SIZE, - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), - /* RAM contains R/W data, non-executable */ -#else /* !CONFIG_XIP */ + MPU_REGION_ENTRY("rom_region", CONFIG_FLASH_BASE_ADDRESS, REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), +/* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ /* .text and .rodata are in RAM, flash is data only -> RO + XN */ MPU_REGIO
You may want to run clang-format on this change: soc/renode/cortex_r8_virtual/arm_mpu_regions.c#L66
soc/renode/cortex_r8_virtual/arm_mpu_regions.c:66 - MPU_REGION_ENTRY( - "vectors", - 0x00000000, - REGION_64B, - {.rasr = P_RO_U_NA_Msk | - NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + MPU_REGION_ENTRY("vectors", 0x00000000, REGION_64B, + {.rasr = P_RO_U_NA_Msk | NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), /* Basic SRAM mapping is all data, R/W + XN */ - MPU_REGION_ENTRY( - "sram", - CONFIG_SRAM_BASE_ADDRESS, - REGION_SRAM_SIZE, - {.rasr = P_RW_U_NA_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("sram", CONFIG_SRAM_BASE_ADDRESS, REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), #if defined(CONFIG_XIP) /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ - MPU_REGION_ENTRY( - "rom_region", - CONFIG_FLASH_BASE_ADDRESS, - REGION_FLASH_SIZE, - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), - /* RAM contains R/W data, non-executable */ -#else /* !CONFIG_XIP */ + MPU_REGION_ENTRY("rom_region", CONFIG_FLASH_BASE_ADDRESS, REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), +/* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ /* .text and .rodata are in RAM, flash is data only -> RO + XN */ MPU_REGION_ENTRY( - "flash", - CONFIG_FLASH_BASE_ADDRESS, - REGION_FLASH_SIZE, - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | - NOT_EXEC}), + "flash", CONFIG_FLASH_BASE_ADDRESS, REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | NOT_EXEC}), /* add rom_region mapping for SRAM which is RO + executable */ - MPU_REGION_ENTRY( - "rom_region", - (uint32_t)(&__rom_region_start), - (uint32_t)(&__rom_region_mpu_size_bits), - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), + MPU_REGION_ENTRY("rom_region", (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), #endif /* CONFIG_XIP */ - MPU_REGION_ENTRY( - "peripherals", - 0xf8000000, - REGION_128M, - {.rasr = P_RW_U_NA_Msk | - DEVICE_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("peripherals", 0xf8000000, REGION_128M, + {.rasr = P_RW_U_NA_Msk | DEVICE_SHAREABLE | NOT_EXEC}),
You may want to run clang-format on this change: soc/xlnx/zynqmp/arm_mpu_regions.c#L73
soc/xlnx/zynqmp/arm_mpu_regions.c:73 - MPU_REGION_ENTRY( - "vectors", - 0x00000000, - REGION_64B, - {.rasr = P_RO_U_NA_Msk | - NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + MPU_REGION_ENTRY("vectors", 0x00000000, REGION_64B, + {.rasr = P_RO_U_NA_Msk | NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), /* Basic SRAM mapping is all data, R/W + XN */ - MPU_REGION_ENTRY( - "sram", - CONFIG_SRAM_BASE_ADDRESS, - REGION_SRAM_SIZE, - {.rasr = P_RW_U_NA_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("sram", CONFIG_SRAM_BASE_ADDRESS, REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), #if defined(CONFIG_XIP) /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ - MPU_REGION_ENTRY( - "rom_region", - CONFIG_FLASH_BASE_ADDRESS, - REGION_FLASH_SIZE, - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), - /* RAM contains R/W data, non-executable */ -#else /* !CONFIG_XIP */ + MPU_REGION_ENTRY("rom_region", CONFIG_FLASH_BASE_ADDRESS, REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), +/* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ /* .text and .rodata are in RAM, flash is data only -> RO + XN */ MPU_REGION_ENTRY( - "flash", - CONFIG_FLASH_BASE_ADDRESS, - REGION_FLASH_SIZE, - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | - NOT_EXEC}), + "flash", CONFIG_FLASH_BASE_ADDRESS, REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | NOT_EXEC}), /* add rom_region mapping for SRAM which is RO + executable */ - MPU_REGION_ENTRY( - "rom_region", - (uint32_t)(&__rom_region_start), - (uint32_t)(&__rom_region_mpu_size_bits), - {.rasr = P_RO_U_RO_Msk | - NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), + MPU_REGION_ENTRY("rom_region", (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), #endif /* CONFIG_XIP */ - MPU_REGION_ENTRY( - "peripherals", - 0xf8000000, - REGION_128M, - {.rasr = P_RW_U_NA_Msk | - DEVICE_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("peripherals", 0xf8000000, REGION_128M, + {.rasr = P_RW_U_NA_Msk | DEVICE_SHAREABLE | NOT_EXEC}), #if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)) && !defined(CONFIG_TEST) - MPU_REGION_ENTRY( - "ocm", - DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)), - REGION_256K, - {.rasr = FULL_ACCESS_Msk | - STRONGLY_ORDERED_SHAREABLE | - NOT_EXEC}), + MPU_REGION_ENTRY("ocm", DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)), REGION_256K, + {.rasr = FULL_ACCESS_Msk | STRONGLY_ORDERED_SHAREABLE | NOT_EXEC}),

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