drivers: intc: plic: allow per-instance support of edge interrupt

Use a devicetree boolean property to allow the support of edge interrupt on a per-instance basis. The "trig" register is now defined in a similar manner like the other registers. Signed-off-by: Yong Cong Sin <[email protected]>
ycsin · Sep 13, 2023 · 96fc5ea · 96fc5ea
1 parent 16518dd
commit 96fc5ea
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Showing 3 changed files with 23 additions and 12 deletions.
diff --git a/drivers/interrupt_controller/Kconfig.plic b/drivers/interrupt_controller/Kconfig.plic
@@ -10,9 +10,3 @@ config PLIC
 	help
 	  Platform Level Interrupt Controller provides support
 	  for external interrupt lines defined by the RISC-V SoC.
-
-config PLIC_SUPPORTS_EDGE_IRQ
-	bool "The given interrupt controller supports edge interrupts"
-	help
-	  The given interrupt controller supports edge triggered
-	  interrupts.
diff --git a/drivers/interrupt_controller/intc_plic.c b/drivers/interrupt_controller/intc_plic.c
@@ -78,7 +78,7 @@ static int riscv_plic_is_edge_irq(uint32_t irq)
 	const struct device *dev = get_plic_dev_from_irq(irq);
 	const struct plic_config *config = dev->config;
 
-	if (IS_ENABLED(CONFIG_PLIC_SUPPORTS_EDGE_IRQ)) {
+	if (config->trig != 0) {
 		volatile uint32_t *trig = (volatile uint32_t *) config->trig;
 
 		trig += (irq >> PLIC_EDGE_TRIG_SHIFT);
@@ -282,14 +282,19 @@ static int plic_init(const struct device *dev)
 		irq_enable(DT_INST_IRQN(n));                                                       \
 	}
 
+#define PLIC_INTC_INIT_TRIG_0(n) 0
+#define PLIC_INTC_INIT_TRIG_1(n) DT_INST_REG_ADDR_BY_NAME(n, trig)
+#define PLIC_INTC_INIT_TRIG(n) \
+	_CONCAT(PLIC_INTC_INIT_TRIG_, DT_INST_PROP(n, support_edge_interrupt))(n)
+
 #define PLIC_INTC_DEVICE_INIT(n)                                                                   \
 	PLIC_INTC_IRQ_FUNC_DECLARE(n);                                                             \
 	static const struct plic_config plic_config_##n = {                                        \
 		.prio = DT_INST_REG_ADDR_BY_NAME(n, prio),                                         \
 		.irq_en = DT_INST_REG_ADDR_BY_NAME(n, irq_en),                                     \
 		.reg = DT_INST_REG_ADDR_BY_NAME(n, reg),                                           \
 		.max_prio = DT_INST_PROP(n, riscv_max_priority),                                   \
-		.trig = DT_INST_PROP(n, riscv_trigger_reg_offset),                                 \
+		.trig = PLIC_INTC_INIT_TRIG(n),                                 \
 		.num_irqs = DT_INST_PROP(n, riscv_ndev),                                           \
 		.irq_config_func = plic_irq_config_func_##n,                                       \
 	};                                                                                         \

diff --git a/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/dts/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -12,7 +12,19 @@ properties:
     type: int
     description: Number of external interrupts supported
     required: true
-  riscv,trigger-reg-offset:
-    type: int
-    default: 4224
-    description: Offset of the trigger type register if supported
+
+  support-edge-interrupt:
+    type: boolean
+    description: |
+      Indicates that this controller supports edge interrupt. When this is enabled,
+      an additional `reg` entry has to be specified and named "trig"for the `trig`
+      register, i.e.:
+      ```
+      reg = <0x0c000000 0x00002000
+             0x0c002000 0x001fe000
+             0x0c200000 0x03e00000
+             0x0c001080 0x00001000>; <--
+             ~~~~~~~~~~~~~~~~~~~~~
+      reg-names = "prio", "irq_en", "reg", "trig";
+                                           ~~~~~~
+      ````