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1. Digital-Design-of-FIR-Filter Digital-Design-of-FIR-Filter Public

   Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Verilog RTL Design and Simulink Testing with .wav audio files.

   Verilog 20 5

2. ASIC-Design-of-Low-Power-Configurable-Multi-Clock-Digital-System-With-UART-Transceiver ASIC-Design-of-Low-Power-Configurable-Multi-Clock-Digital-System-With-UART-Transceiver Public

   RTL to GDS|| Implementation of a Digital System supporting Read, Write, Low-Power ALU Operation With/Without Operand Commands through core blocks operation with 50 MHz interfaced with 6.9 KHz UART …

   Verilog 1

3. 32-bit-Single-Cycle-RISC-V 32-bit-Single-Cycle-RISC-V Public

   Digital Design and Verification of 32-bit Single Cycle RISC-V Processor using Verilog HDL and Xilinx Vivado

   Verilog 3

4. sheshtawy898/GPS_ASU_PROJECT_67 sheshtawy898/GPS_ASU_PROJECT_67 Public

   GPS tracking system

   C 4 2

5. YaseenSalah.me YaseenSalah.me Public

   Personal Website

   CSS