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Merge pull request #492 from xmos/bugfix/rtos_driver_test_io_voltage_fix
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Fixes gpio pin and updates uart test for stdpinout
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xmos-jmccarthy authored Jul 7, 2022
2 parents 9364b5c + 664bc5b commit 78d12c8
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Showing 10 changed files with 277 additions and 149 deletions.
24 changes: 12 additions & 12 deletions test/rtos_drivers/hil/README.rst
Original file line number Diff line number Diff line change
Expand Up @@ -24,20 +24,20 @@ The target hardware for these tests is the XCORE-AI-EXPLORER board.

To setup the board for testing, the following connections must be made:

============ ================
Pin Desc Connection
============ ================
GPIO I/O X1D12 : X1D39
I2C SCL SCL IOL : X1D36
I2C SDA SDA IOL : X1D38
I2S DACD DAC_DAT : X0D12
I2S ADCD ADC_DAT : X0D13
I2S BCLK BCLK : X0D22
I2S LRCLK LRCLK : X0D23
============ ================
============ ================ ================ =====================================
Pin Desc hil Pin Desc hil_add Connection Port Name
============ ================ ================ =====================================
GPIO I/O Unused X1D02 : X1D39 T1 XS1_PORT_4A Pin 0 : T1 XS1_PORT_1P
I2C SCL UART TX/RX SCL IOL : X1D36 T0 XS1_PORT_1N : T1 XS1_PORT_1M
I2C SDA SPI CS SDA IOL : X1D38 T0 XS1_PORT_1O : T1 XS1_PORT_1O
I2S DACD SPI MOSI DAC_DAT : X0D12 T1 XS1_PORT_1A : T0 XS1_PORT_1E
I2S ADCD SPI MISO ADC_DAT : X0D13 T1 XS1_PORT_1N : T0 XS1_PORT_1F
I2S BCLK Unused BCLK : X0D22 T1 XS1_PORT_1C : T0 XS1_PORT_1G
I2S LRCLK SPI SCLK LRCLK : X0D23 T1 XS1_PORT_1B : T0 XS1_PORT_1H
============ ================ ================ =====================================

Wiring Diagram
==============

.. image:: images/wiring_diagram.png
:align: left
:align: left
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,7 @@ typedef int (*gpio_main_test_t)(gpio_test_ctx_t *ctx);
#define INPUT_PORT XS1_PORT_1P
#define INPUT_PORT_PIN_OFFSET 0

#define OUTPUT_PORT XS1_PORT_1E
#define OUTPUT_PORT XS1_PORT_4A
#define OUTPUT_PORT_PIN_OFFSET 0

int gpio_device_tests(rtos_gpio_t *gpio_ctx, chanend_t c);
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1 change: 1 addition & 0 deletions test/rtos_drivers/hil/src/individual_tests/i2c/i2c_test.c
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
/* System headers */
#include <platform.h>
#include <xs1.h>
#include <string.h>

/* FreeRTOS headers */
#include "FreeRTOS.h"
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1 change: 1 addition & 0 deletions test/rtos_drivers/hil_add/README.rst
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ RTOS Driver Additional Tests
The RTOS driver tests are designed to regression test RTOS driver behavior for the following drivers:

- spi
- uart

These tests assume that the associated RTOS and HILs used have been verified by their own localized separate testing.

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33 changes: 16 additions & 17 deletions test/rtos_drivers/hil_add/src/board_init.c
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,8 @@ void board_tile0_init(
chanend_t tile1,
rtos_intertile_t *intertile_ctx,
rtos_spi_master_t *spi_master_ctx,
rtos_spi_master_device_t *test_device_ctx
rtos_spi_master_device_t *test_device_ctx,
rtos_uart_tx_t *rtos_uart_tx_ctx
)
{
rtos_intertile_init(intertile_ctx, tile1);
Expand Down Expand Up @@ -51,6 +52,18 @@ void board_tile0_init(
&spi_master_rpc_config,
client_intertile_ctx,
1);

hwtimer_t tmr_tx = hwtimer_alloc();

rtos_uart_tx_init(
rtos_uart_tx_ctx,
XS1_PORT_1N,
UART_BAUD_RATE,
8,
UART_PARITY_ODD,
1,
tmr_tx);

}

void board_tile1_init(
Expand All @@ -59,8 +72,7 @@ void board_tile1_init(
rtos_spi_master_t *spi_master_ctx,
rtos_spi_master_device_t *test_device_ctx,
rtos_spi_slave_t *spi_slave_ctx,
rtos_uart_tx_t *rtos_uart_tx_ctx,
rtos_uart_rx_t *rtos_uart_rx_ctx
rtos_uart_rx_t *rtos_uart_rx_ctx
)
{
rtos_intertile_init(intertile_ctx, tile0);
Expand All @@ -85,25 +97,12 @@ void board_tile1_init(
&spi_master_rpc_config,
intertile_ctx);


hwtimer_t tmr_tx = hwtimer_alloc();

rtos_uart_tx_init(
rtos_uart_tx_ctx,
XS1_PORT_1P, /* X1D39 */
UART_BAUD_RATE,
8,
UART_PARITY_ODD,
1,
tmr_tx);


hwtimer_t tmr_rx = hwtimer_alloc();

rtos_uart_rx_init(
rtos_uart_rx_ctx,
UART_RX_CORE_MASK,
XS1_PORT_1M , /* X1D36 */
XS1_PORT_1M ,
UART_BAUD_RATE,
8,
UART_PARITY_ODD,
Expand Down
6 changes: 3 additions & 3 deletions test/rtos_drivers/hil_add/src/board_init.h
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,8 @@ void board_tile0_init(
chanend_t tile1,
rtos_intertile_t *intertile_ctx,
rtos_spi_master_t *spi_master_ctx,
rtos_spi_master_device_t *test_device_ctx
rtos_spi_master_device_t *test_device_ctx,
rtos_uart_tx_t *rtos_uart_tx_ctx
);

void board_tile1_init(
Expand All @@ -23,8 +24,7 @@ void board_tile1_init(
rtos_spi_master_t *spi_master_ctx,
rtos_spi_master_device_t *test_device_ctx,
rtos_spi_slave_t *spi_slave_ctx,
rtos_uart_tx_t *rtos_uart_tx_ctx,
rtos_uart_rx_t *rtos_uart_rx_ctx
rtos_uart_rx_t *rtos_uart_rx_ctx
);

#endif /* BOARD_INIT_H_ */
Original file line number Diff line number Diff line change
@@ -0,0 +1,155 @@
// Copyright 22022 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.

/* System headers */
#include <platform.h>
#include <xs1.h>
#include <string.h>

/* FreeRTOS headers */
#include "FreeRTOS.h"

/* Library headers */
#include "rtos_uart_tx.h"
#include "rtos_uart_rx.h"

/* App headers */
#include "app_conf.h"
#include "individual_tests/uart/uart_test.h"

#if ON_TILE(UART_RX_TILE)
static volatile int error_cb_occurred = 0;

UART_RX_STARTED_ATTR
void rx_started(rtos_uart_rx_t *ctx){
uart_printf("rtos_uart_rx_started_cb");
}

UART_RX_ERROR_ATTR
void rx_error(rtos_uart_rx_t *ctx, uint8_t err_flags){

uart_printf("rtos_uart_rx_error:");
if(err_flags & UR_START_BIT_ERR_CB_FLAG){
uart_printf("UART_START_BIT_ERROR");
}
if(err_flags & UR_PARITY_ERR_CB_FLAG){
uart_printf("UART_PARITY_ERROR");
}
if(err_flags & UR_FRAMING_ERR_CB_FLAG){
uart_printf("UART_FRAMING_ERROR");
}
if(err_flags & UR_OVERRUN_ERR_CB_FLAG){
uart_printf("UR_OVERRUN_ERR_CB_CODE");
}

if(err_flags & ~ RX_ERROR_FLAGS){
uart_printf("UNKNOWN ERROR FLAG SET: 0x%x (THIS SHOULD NEVER HAPPEN)", err_flags);
}

error_cb_occurred = 1;
}

UART_RX_COMPLETE_ATTR
void rx_complete(rtos_uart_rx_t *ctx){
// uart_printf("UART_RX_COMPLETE\n");
// The backpressure from this causes a test fail - WHY?
}
#endif

static const char* test_name = "uart_loopback_test";

UART_MAIN_TEST_ATTR
static int main_test(uart_test_ctx_t *ctx)
{
int retval = 0;
const unsigned num_packets = 100;
const uint8_t tx_buff[] = {0xed, 0x00, 0x77, 0xed, 0x00, 0x77, 0xed, 0x00, 0x55, 0x55, 0xff, 0x55,
0xed, 0x00, 0x77, 0xed, 0x00, 0x77, 0xed, 0x00, 0x55, 0x55, 0xff, 0x55,
0xed, 0x00, 0x77, 0xed, 0x00, 0x77, 0xed, 0x00, 0x55, 0x55, 0xff, 0x55,
0xed, 0x00, 0x77, 0xed, 0x00, 0x77, 0xed, 0x00, 0x55, 0x55, 0xff, 0x55,
0xed, 0x00, 0x77, 0xed, 0x00, 0x77, 0xed, 0x00, 0x55, 0x55, 0xff, 0x55 };//6 x 12 = 72B

#if ON_TILE(UART_TX_TILE)
for(unsigned t = 0; t < num_packets; t++)
{
rtos_uart_tx_write(ctx->rtos_uart_tx_ctx, tx_buff, sizeof(tx_buff));
vTaskDelay(pdMS_TO_TICKS(1));
}
#endif

#if ON_TILE(UART_RX_TILE)
for(unsigned t = 0; t < num_packets; t++)
{
uint8_t rx_buff[sizeof(tx_buff)] = {0};
memset(rx_buff, 0x11, sizeof(rx_buff));

size_t num_read_tot = 0;
size_t num_timeouts = 0;
while(num_read_tot < sizeof(rx_buff) && num_timeouts == 0){
size_t num_rx = xStreamBufferReceive(ctx->rtos_uart_rx_ctx->app_byte_buffer,
&rx_buff[num_read_tot],
sizeof(rx_buff),
pdMS_TO_TICKS(100));
num_read_tot += num_rx;
num_timeouts += (num_rx == 0);
}

int length_same = (num_read_tot == sizeof(tx_buff));
int array_different = memcmp(tx_buff, rx_buff, sizeof(tx_buff));
if(!length_same || array_different){
uart_printf("uart loopback result len: %s, contents: %s", length_same ? "PASS" : "FAIL", array_different ? "FAIL" : "PASS");
}
if(!length_same){
uart_printf("len expected: %d, actual: %d", sizeof(tx_buff), num_read_tot);
retval = -1;
}
if(array_different){
for(int i = 0; i < sizeof(tx_buff); i++){
if(rx_buff[i] != tx_buff[i]){
uart_printf("Rx byte %d got: 0x%x exp: 0x%x", i, rx_buff[i], tx_buff[i]);
}
}
retval = -1;
}
}

if(error_cb_occurred){
retval = -1;
error_cb_occurred = 0;
ctx->rx_success[ctx->cur_test] = 0;
}

if (ctx->rx_success[ctx->cur_test] != 0)
{
uart_printf("RX failed");
}
#endif

return retval;
}

void register_local_loopback_test(uart_test_ctx_t *test_ctx)
{
uint32_t this_test_num = test_ctx->test_cnt;

uart_printf("Register to test num %d", this_test_num);

test_ctx->name[this_test_num] = (char*)test_name;
test_ctx->main_test[this_test_num] = main_test;

#if ON_TILE(UART_RX_TILE)
test_ctx->uart_rx_started[this_test_num] = rx_started;
test_ctx->uart_rx_error[this_test_num] = rx_error;
test_ctx->uart_rx_complete[this_test_num] = rx_complete;
#endif

#if ON_TILE(UART_TX_TILE)
test_ctx->uart_rx_started[this_test_num] = NULL;
test_ctx->uart_rx_error[this_test_num] = NULL;
test_ctx->uart_rx_complete[this_test_num] = NULL;
#endif

test_ctx->rx_success[this_test_num] = 0;

test_ctx->test_cnt++;
}
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