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Merge pull request #101 from ACascarino/enhancement/ap316_16b_data
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hotfix: add subst. in I2S doc, move decl. in tests
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ACascarino authored Feb 9, 2024
2 parents b924f4f + 2bf354c commit 0ecba51
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6 changes: 3 additions & 3 deletions doc/programming_guide/reference/i2s/i2s_common.rst
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Expand Up @@ -7,9 +7,9 @@
===============

The macro I2S_DATA_WIDTH may be set as a compile flag (e.g.
-DI2S_DATA_WIDTH=16) to alter the number of bits per word for both the I2S
Master and I2S Slave components; this defaults to 32 bits per word. This
value may be set to any value between 1 and 32. Correct operation of the I2S
-DI2S_DATA_WIDTH=16) to alter the number of bits per word for both the |I2S|
Master and |I2S| Slave components; this defaults to 32 bits per word. This
value may be set to any value between 1 and 32. Correct operation of the |I2S|
components has only currently been verified at 16 and 32 bits per word.

The following structures and functions are used by an |I2S| master or slave instance.
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3 changes: 2 additions & 1 deletion test/lib_i2s/i2s_slave_checker.py
Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,6 @@ def run(self):
f"CONFIG: bclk:{bclk_frequency} in:{num_ins} out:{num_outs} data_bits: {data_bits} i2s_justified:{is_i2s_justified}"
)
clock_half_period = float(ONE_SECOND_FS) / float(2 * bclk_frequency)
data_bit_mask = int("1" * data_bits, base=2)

if self._invert_bclk:
bclk0 = 1
Expand Down Expand Up @@ -214,6 +213,8 @@ def run(self):
time = self.wait_until_ret(
time + clock_half_period - din_sample_offset
)

data_bit_mask = int("1" * data_bits, base=2)

for p in range(0, num_outs):
if (data_bit_mask & rx_data[p * 2][frame_count]) != rx_word[p]:
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