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Missing unsafe
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vigna committed Nov 25, 2024
1 parent fdaac1d commit 606568d
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions src/utils/sync_slice.rs
Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,7 @@ impl<T> SyncCell<T> {
/// same time. It is responsibility of the user to ensure that there are no
/// data races, which would cause undefined behavior.
#[inline]
pub fn replace(&self, val: T) -> T {
pub unsafe fn replace(&self, val: T) -> T {
self.0.replace(val)
}

Expand All @@ -156,7 +156,7 @@ impl<T: Copy> SyncCell<T> {
/// same time. It is responsibility of the user to ensure that there are no
/// data races, which would cause undefined behavior.
#[inline]
pub fn get(&self) -> T {
pub unsafe fn get(&self) -> T {
self.0.get()
}
}
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