Fix warnings (#4)

* Fix all warnings

* Fix all warnings in examples

* fmt

* More clippy warnings

* Fix more warnings

examples/can-echo.rs

@@ -120,7 +120,7 @@ fn main() -> ! {
 
     loop {
         if let Ok(rxheader) = block!(can.receive0(&mut buffer)) {
-            block!(can.transmit(rxheader.unwrap().to_tx_header(None), &mut buffer)).unwrap();
+            block!(can.transmit(rxheader.unwrap().to_tx_header(None), &buffer)).unwrap();
         }
     }
 }

examples/i2c-bme680.rs

@@ -52,15 +52,15 @@ fn main() -> ! {
         .with_run_gas(true)
         .build();
 
-    let profile_dur = dev.get_profile_dur(&settings.0).unwrap();
+    let _profile_dur = dev.get_profile_dur(&settings.0).unwrap();
     dev.set_sensor_settings(&mut delayer, settings).unwrap();
     dev.set_sensor_mode(&mut delayer, PowerMode::ForcedMode)
         .unwrap();
-    let sensor_settings = dev.get_sensor_settings(settings.1);
+    let _sensor_settings = dev.get_sensor_settings(settings.1);
 
     loop {
         delay.delay_ms(500u32);
-        let power_mode = dev.get_sensor_mode();
+        let _power_mode = dev.get_sensor_mode();
         dev.set_sensor_mode(&mut delayer, PowerMode::ForcedMode)
             .unwrap();
         let (data, _state) = dev.get_sensor_data(&mut delayer).unwrap();

examples/panic.rs

@@ -7,8 +7,6 @@ use panic_probe as _;
 
 use stm32g4 as _;
 
-use defmt::Format;
-
 #[defmt::panic_handler]
 fn panic() -> ! {
     cortex_m::asm::udf()

examples/pwm.rs

@@ -10,11 +10,15 @@ use hal::prelude::*;
 use hal::stm32;
 use hal::time::RateExtU32;
 use stm32g4xx_hal as hal;
-mod utils;
 extern crate cortex_m_rt as rt;
 
+#[macro_use]
+mod utils;
+
 #[entry]
 fn main() -> ! {
+    utils::logger::init();
+
     let dp = stm32::Peripherals::take().expect("cannot take peripherals");
     let mut rcc = dp.RCC.constrain();
     let gpioa = dp.GPIOA.split(&mut rcc);

examples/spi-sd.rs

@@ -7,32 +7,28 @@ extern crate embedded_sdmmc;
 
 use hal::gpio::gpiob::PB14;
 use hal::gpio::gpiob::PB15;
-use hal::gpio::gpiof::PF8;
 use hal::gpio::gpiof::PF9;
 use hal::gpio::Alternate;
 use hal::gpio::AF5;
 use hal::prelude::*;
 use hal::rcc::Config;
 use hal::spi;
-use hal::stm32;
+
 use hal::stm32::Peripherals;
 use hal::time::RateExtU32;
-use hal::timer::Timer;
 use stm32g4xx_hal as hal;
 
-use embedded_sdmmc::{
-    Block, BlockCount, BlockDevice, BlockIdx, Controller, Error, Mode, TimeSource, Timestamp,
-    VolumeIdx,
-};
+use embedded_sdmmc::{TimeSource, Timestamp};
 
 use cortex_m_rt::entry;
-use log::info;
 
 #[macro_use]
 mod utils;
 
 #[entry]
 fn main() -> ! {
+    utils::logger::init();
+
     let dp = Peripherals::take().unwrap();
     let rcc = dp.RCC.constrain();
     let mut rcc = rcc.freeze(Config::hsi());
@@ -49,7 +45,7 @@ fn main() -> ! {
     let miso: PB14<Alternate<AF5>> = gpiob.pb14.into_alternate();
     let mosi: PB15<Alternate<AF5>> = gpiob.pb15.into_alternate();
 
-    let mut spi = dp
+    let spi = dp
         .SPI2
         .spi((sck, miso, mosi), spi::MODE_0, 400.kHz(), &mut rcc);
 
@@ -70,6 +66,8 @@ fn main() -> ! {
 
     let mut cont = embedded_sdmmc::Controller::new(embedded_sdmmc::SdMmcSpi::new(spi, cs), Clock);
 
-    cont.device().init();
+    cont.device().init().unwrap();
+
+    #[allow(clippy::empty_loop)]
     loop {}
 }

examples/utils/logger.rs

@@ -55,7 +55,6 @@ cfg_if::cfg_if! {
         impl log::Log for Logger {
             fn enabled(&self, metadata: &Metadata) -> bool {
                 metadata.level() <= self.level
-
             }
 
             fn log(&self, record: &Record) {

src/adc.rs

@@ -559,7 +559,7 @@ pub mod config {
     }
 
     /// Sets the input type per channel
-    #[derive(Debug, Clone, Copy)]
+    #[derive(Debug, Clone, Copy, Default)]
     pub struct DifferentialSelection(pub(crate) u32);
     impl DifferentialSelection {
         /// Set pin to Single-Ended or Differential
@@ -602,12 +602,6 @@ pub mod config {
         }
     }
 
-    impl Default for DifferentialSelection {
-        fn default() -> Self {
-            DifferentialSelection(0)
-        }
-    }
-
     /// Configuration for the adc.
     /// There are some additional parameters on the adc peripheral that can be
     /// added here when needed but this covers several basic usecases.

src/can.rs

@@ -12,6 +12,7 @@ mod sealed {
 }
 
 /// Select an FDCAN Clock Source
+#[allow(clippy::upper_case_acronyms)]
 #[allow(dead_code)]
 enum FdCanClockSource {
     /// Select HSE as the FDCAN clock source

src/dma/config.rs

@@ -4,22 +4,18 @@ use super::Bits;
 /// the same software priority level, the stream with the lower number takes
 /// priority over the stream with the higher number. For example, Stream 2
 /// takes priority over Stream 4.
-#[derive(Debug, Clone, Copy)]
+#[derive(Debug, Clone, Copy, Default)]
 pub enum Priority {
     /// Low priority.
     Low,
     /// Medium priority.
+    #[default]
     Medium,
     /// High priority.
     High,
     /// Very high priority.
     VeryHigh,
 }
-impl Default for Priority {
-    fn default() -> Self {
-        Priority::Medium
-    }
-}
 
 impl Bits<u8> for Priority {
     fn bits(self) -> u8 {

src/dma/mux.rs

@@ -1,3 +1,4 @@
+#[allow(clippy::upper_case_acronyms)]
 pub enum DmaMuxResources {
     DMAMUXReqG0 = 1,
     DMAMUXReqG1 = 2,

src/dma/transfer.rs

@@ -313,7 +313,7 @@ where
 {
     /// Return the number of elements available to read
     pub fn elements_available(&mut self) -> usize {
-        let blen = unsafe { self.transfer.buf.static_write_buffer().1 } as usize;
+        let blen = unsafe { self.transfer.buf.static_write_buffer().1 };
         let ndtr = STREAM::get_number_of_transfers() as usize;
         let pos_at = self.r_pos;
 
@@ -341,7 +341,7 @@ where
         &mut self,
         dat: &mut [<PERIPHERAL as TargetAddress<PeripheralToMemory>>::MemSize],
     ) -> usize {
-        let blen = unsafe { self.transfer.buf.static_write_buffer().1 } as usize;
+        let blen = unsafe { self.transfer.buf.static_write_buffer().1 };
         let pos = self.r_pos;
         let read = dat.len();
 

src/flash.rs

@@ -108,7 +108,7 @@ impl<'a, const SECTOR_SZ_KB: u32> FlashWriter<'a, SECTOR_SZ_KB> {
         if offset
             .checked_add(length as u32)
             .ok_or(Error::LengthTooLong)?
-            > self.flash_sz.kbytes() as u32
+            > self.flash_sz.kbytes()
         {
             Err(Error::LengthTooLong)
         } else if length & 0x1 != 0 {
@@ -128,7 +128,7 @@ impl<'a, const SECTOR_SZ_KB: u32> FlashWriter<'a, SECTOR_SZ_KB> {
         // Set Page Erase
         self.flash.cr.cr().modify(|_, w| w.per().set_bit());
 
-        let page = start_offset / (SECTOR_SZ_KB as u32);
+        let page = start_offset / SECTOR_SZ_KB;
 
         // Write address bits
         // NOTE(unsafe) This sets the page address in the Address Register.
@@ -170,7 +170,7 @@ impl<'a, const SECTOR_SZ_KB: u32> FlashWriter<'a, SECTOR_SZ_KB> {
                 let size = SECTOR_SZ_KB;
                 let start = start_offset & !(size - 1);
                 for idx in (start..start + size).step_by(2) {
-                    let write_address = (FLASH_START + idx as u32) as *const u16;
+                    let write_address = (FLASH_START + idx) as *const u16;
                     let verify: u16 = unsafe { core::ptr::read_volatile(write_address) };
                     if verify != 0xFFFF {
                         return Err(Error::VerifyError);
@@ -201,7 +201,7 @@ impl<'a, const SECTOR_SZ_KB: u32> FlashWriter<'a, SECTOR_SZ_KB> {
     pub fn read(&self, offset: u32, length: usize) -> Result<&[u8]> {
         self.valid_address(offset)?;
 
-        if offset + length as u32 > self.flash_sz.kbytes() as u32 {
+        if offset + length as u32 > self.flash_sz.kbytes() {
             return Err(Error::LengthTooLong);
         }
 
@@ -324,6 +324,7 @@ pub struct Parts {
     pub(crate) cr: CR,
 
     /// Opaque ECCR register
+    #[allow(unused)]
     pub(crate) eccr: ECCR,
 
     /// Opaque KEYR register
@@ -342,9 +343,11 @@ pub struct Parts {
     pub(crate) _pcrop1er: PCROP1ER,
 
     /// Opaque PDKEYR register
+    #[allow(unused)]
     pub(crate) pdkeyr: PDKEYR,
 
     /// Opaque SEC1R register
+    #[allow(unused)]
     pub(crate) sec1r: SEC1R,
 
     /// Opaque SR register

src/i2c.rs

@@ -1,8 +1,16 @@
 //! I2C
 use hal::blocking::i2c::{Read, Write, WriteRead};
 
-use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiof::*, gpiog::*};
-use crate::gpio::{AlternateOD, AF2, AF3, AF4, AF8};
+use crate::gpio::{gpioa::*, gpiob::*, gpioc::*, gpiof::*};
+#[cfg(any(
+    feature = "stm32g471",
+    feature = "stm32g473",
+    feature = "stm32g474",
+    feature = "stm32g483",
+    feature = "stm32g484"
+))]
+use crate::gpio::{gpiog::*, AF3};
+use crate::gpio::{AlternateOD, AF2, AF4, AF8};
 use crate::rcc::{Enable, GetBusFreq, Rcc, RccBus, Reset};
 #[cfg(any(
     feature = "stm32g471",

src/pwm.rs

@@ -1080,7 +1080,7 @@ fn calculate_deadtime(base_freq: Hertz, deadtime: NanoSecond) -> (u8, u8) {
     let deadtime_ticks = deadtime_ticks as u64 * 429497;
     let deadtime_ticks = (deadtime_ticks >> 32) as u32;
 
-    let deadtime_ticks = deadtime_ticks as u32;
+    let deadtime_ticks = deadtime_ticks;
 
     // Choose CR1 CKD divider of 1, 2, or 4 to determine tDTS
     let (deadtime_ticks, ckd) = match deadtime_ticks {

src/rcc/config.rs

@@ -71,11 +71,11 @@ pub enum PllMDiv {
 
 impl PllMDiv {
     pub fn divisor(&self) -> u32 {
-        (self.clone() as u32) + 1
+        (*self as u32) + 1
     }
 
     pub fn register_setting(&self) -> u8 {
-        self.clone() as u8
+        *self as u8
     }
 }
 
@@ -90,11 +90,11 @@ pub enum PllQDiv {
 
 impl PllQDiv {
     pub fn divisor(&self) -> u32 {
-        ((self.clone() as u32) + 1) * 2
+        ((*self as u32) + 1) * 2
     }
 
     pub fn register_setting(&self) -> u8 {
-        self.clone() as u8
+        *self as u8
     }
 }
 
@@ -109,11 +109,11 @@ pub enum PllRDiv {
 
 impl PllRDiv {
     pub fn divisor(&self) -> u32 {
-        ((self.clone() as u32) + 1) * 2
+        ((*self as u32) + 1) * 2
     }
 
     pub fn register_setting(&self) -> u8 {
-        self.clone() as u8
+        *self as u8
     }
 }
 
@@ -158,11 +158,11 @@ pub enum PllPDiv {
 
 impl PllPDiv {
     pub fn divisor(&self) -> u32 {
-        self.clone() as u32
+        *self as u32
     }
 
     pub fn register_setting(&self) -> u8 {
-        self.clone() as u8
+        *self as u8
     }
 }
 
@@ -293,11 +293,11 @@ pub enum PllNMul {
 
 impl PllNMul {
     pub fn multiplier(&self) -> u32 {
-        self.clone() as u32
+        *self as u32
     }
 
     pub fn register_setting(&self) -> u8 {
-        self.clone() as u8
+        *self as u8
     }
 }