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verilog-a

Here are 15 public repositories matching this topic...

pascalkuthe / OpenVAF

An innovative Verilog-A compiler

rust compiler eda verilog-a

Updated Aug 20, 2024
Rust

dwarning / VA-Models

Verilog-A simulation models

simulation modelling ngspice xyce verilog-a qucs-s

Updated Nov 22, 2024
Pascal

ColsonZhang / VerilogA-Wave-Generator

The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.

simulation cadence-virtuoso virtuoso verilog-a waveform-generator veriloga

Updated Feb 10, 2022
Python

ACMmodel / MOSFET_model

A simple MOSFET model with only 5-DC-parameters for circuit simulation

open-source mosfet verilog-a sky130 ihp transistor-modeling icdesign gf180mcu circuitsimulation

Updated Jun 25, 2024

akashlevy / pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

python generator simulation waveform nvm spice circuit testbench netlist hspice verilog-a rram memory-design

Updated Jan 22, 2020
SourcePawn

akashlevy / WP-RRAM-SPICE-Model

A well-posed RRAM SPICE model implemented in Verilog-A, based on Stanford/ASU filamentary model, using code developed at UC Berkeley

verilog-a compact-model rram veriloga spice-model well-posed

Updated Nov 30, 2020

gnucap / gnucap-adms

defunct. use repo on savannah

gnucap adms verilog-a

Updated Nov 13, 2018

pouryahoseini / Genetic-Algorithm-Processor

A digital genetic algorithm processor

digital optimization processor genetic-algorithm spice circuit evolutionary-computation cmos verilog-a hsim customsim

Updated Apr 10, 2020
Verilog

Synaptogen

thennen / Synaptogen

A fast generative model for stochastic memory cells

machine-learning simulation gpu julia modeling circuit-simulation neuromorphic-hardware verilog-a reram emerging-technology

Updated Oct 9, 2024
Julia

NVerilog / NVerilogParser

A Verilog-AMS parser for .NET

parser csharp dotnet verilog verilog-a verilog-ams

Updated Sep 1, 2022
C#

rpm2003rpm / vagen

Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)

generator simulation waveform testbench cadence-virtuoso cadence verilog-a waveform-generator testbench-generator veriloga verilog-ams

Updated Apr 9, 2024
Python

pyadms / pyadms

Python Automatic Device Model Synthesizer

python verilog-a verilog-ams

Updated Feb 26, 2024
C++

rpm2003rpm / stg2veriloga

converts a stg (.g file generated by workcraft) to a verilogA model

generator simulation asynchronous stg digital-logic-design verilog-a

Updated Aug 4, 2024
Python

posvirus / RTE-Sim

Compact model for light propagation simulation in fNIRS systems

simulink fnirs verilog-a compactmodelling

Updated Mar 18, 2024

nikacvet / vscode-verilogA

Language support in Visual Studio Code for VerilogA

syntax-highlighting visual-studio-code vscode-extension verilog-a veriloga

Updated May 24, 2024
TypeScript

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