ace: overlay: update clock frequency

Changing max clock frequency for FPGA configuration. Signed-off-by: Tomasz Leman <[email protected]>
thesofproject · Sep 20, 2023 · dda42d4 · dda42d4
1 parent 29128db
commit dda42d4
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diff --git a/app/overlays/lnl/fpga_overlay.conf b/app/overlays/lnl/fpga_overlay.conf
@@ -1,2 +1,3 @@
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
 CONFIG_DAI_DMIC_HW_IOCLK=19200000
+CONFIG_XTENSA_CCOUNT_HZ=40000000
diff --git a/app/overlays/mtl/fpga_overlay.conf b/app/overlays/mtl/fpga_overlay.conf
@@ -1,2 +1,3 @@
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000
 CONFIG_DAI_DMIC_HW_IOCLK=19200000
+CONFIG_XTENSA_CCOUNT_HZ=40000000