Merge branch 'mt8186/v0.2' into mt8186/v0.2

Signed-off-by: Barry Jan <[email protected]>

src/audio/module_adapter/module/cadence.c

@@ -653,7 +653,6 @@ cadence_codec_process(struct processing_module *mod,
 
 static int cadence_codec_reset(struct processing_module *mod)
 {
-	struct comp_dev *dev = mod->dev;
 	struct module_data *codec = &mod->priv;
 	struct cadence_codec_data *cd = codec->private;
 	int ret;
@@ -675,12 +674,6 @@ static int cadence_codec_reset(struct processing_module *mod)
 	rfree(cd->self);
 	cd->self = NULL;
 
-	ret = cadence_codec_prepare(mod);
-	if (ret) {
-		comp_err(dev, "cadence_codec_reset() error %x: could not re-prepare codec after reset",
-			ret);
-	}
-
 	return ret;
 }
 

src/audio/module_adapter/module/generic.c

@@ -279,11 +279,13 @@ int module_reset(struct processing_module *mod)
 	md->cfg.avail = false;
 	md->cfg.size = 0;
 	rfree(md->cfg.data);
+	md->cfg.data = NULL;
 
-	/* module resets itself to the initial condition after prepare()
-	 * so let's change its state to reflect that.
+	/*
+	 * reset the state to allow the module's prepare callback to be invoked again for the
+	 * subsequent triggers
 	 */
-	md->state = MODULE_IDLE;
+	md->state = MODULE_INITIALIZED;
 
 	return 0;
 }
@@ -317,9 +319,11 @@ int module_free(struct processing_module *mod)
 	md->cfg.avail = false;
 	md->cfg.size = 0;
 	rfree(md->cfg.data);
-	if (md->runtime_params)
+	md->cfg.data = NULL;
+	if (md->runtime_params) {
 		rfree(md->runtime_params);
-
+		md->runtime_params = NULL;
+	}
 	md->state = MODULE_DISABLED;
 
 	return ret;

src/audio/module_adapter/module/passthrough.c

@@ -96,22 +96,20 @@ passthrough_codec_process(struct processing_module *mod,
 
 static int passthrough_codec_reset(struct processing_module *mod)
 {
+	struct module_data *codec = &mod->priv;
+
 	comp_info(mod->dev, "passthrough_codec_reset()");
 
-	/* nothing to do */
+	rfree(codec->mpd.in_buff);
+	rfree(codec->mpd.out_buff);
 	return 0;
 }
 
 static int passthrough_codec_free(struct processing_module *mod)
 {
-	struct comp_dev *dev = mod->dev;
-	struct module_data *codec = &mod->priv;
-
 	comp_info(dev, "passthrough_codec_free()");
 
-	rfree(codec->mpd.in_buff);
-	rfree(codec->mpd.out_buff);
-
+	/* Nothing to do */
 	return 0;
 }
 

src/audio/module_adapter/module/waves.c

@@ -828,6 +828,12 @@ static int waves_codec_reset(struct processing_module *mod)
 	if (ret)
 		comp_err(dev, "waves_codec_reset() failed %d", ret);
 
+	if (codec->mpd.in_buff)
+		module_free_memory(mod, codec->mpd.in_buff);
+
+	if (codec->mpd.out_buff)
+		module_free_memory(mod, codec->mpd.out_buff);
+
 	comp_dbg(dev, "waves_codec_reset() done");
 	return ret;
 }

src/audio/module_adapter/module_adapter.c

@@ -128,6 +128,7 @@ int module_adapter_prepare(struct comp_dev *dev)
 	int ret;
 	struct processing_module *mod = comp_get_drvdata(dev);
 	struct module_data *md = &mod->priv;
+	struct comp_buffer *sink;
 	struct list_item *blist, *_blist;
 	uint32_t buff_periods;
 	uint32_t buff_size; /* size of local buffer */
@@ -145,6 +146,13 @@ int module_adapter_prepare(struct comp_dev *dev)
 		return PPL_STATUS_PATH_STOP;
 	}
 
+	/* Get period_bytes first on prepare(). At this point it is guaranteed that the stream
+	 * parameter from sink buffer is settled, and still prior to all references to period_bytes.
+	 */
+	sink = list_first_item(&dev->bsink_list, struct comp_buffer, source_list);
+	mod->period_bytes = audio_stream_period_bytes(&sink->stream, dev->frames);
+	comp_dbg(dev, "module_adapter_prepare(): got period_bytes = %u", mod->period_bytes);
+
 	/* Prepare module */
 	ret = module_prepare(mod);
 	if (ret) {
@@ -360,8 +368,6 @@ int module_adapter_params(struct comp_dev *dev, struct sof_ipc_stream_params *pa
 			return ret;
 	}
 
-	mod->period_bytes = params->sample_container_bytes *
-			   params->channels * params->rate / 1000;
 	return 0;
 }
 

src/include/ipc/dai.h

@@ -89,8 +89,8 @@ enum sof_ipc_dai_type {
 	SOF_DAI_AMD_BT,			/**< Amd BT */
 	SOF_DAI_AMD_SP,			/**< Amd SP */
 	SOF_DAI_AMD_DMIC,		/**< Amd DMIC */
+	SOF_DAI_MEDIATEK_AFE,           /**< Mtk AFE */
 	SOF_DAI_AMD_HS,			/**< Amd HS */
-	SOF_DAI_MEDIATEK_AFE            /**< Mtk AFE */
 };
 
 /* general purpose DAI configuration */

src/include/sof/audio/module_adapter/module/generic.h

@@ -190,12 +190,12 @@ struct module_interface {
 	/**
 	 * Module specific reset procedure, called as part of module_adapter component
 	 * reset in .reset(). This should reset all parameters to their initial stage
-	 * but leave allocated memory intact.
+	 * and free all memory allocated during prepare().
 	 */
 	int (*reset)(struct processing_module *mod);
 	/**
 	 * Module specific free procedure, called as part of module_adapter component
-	 * free in .free(). This should free all memory allocated by module.
+	 * free in .free(). This should free all memory allocated during module initialization.
 	 */
 	int (*free)(struct processing_module *mod);
 };

src/platform/mt8186/include/platform/lib/clk.h

@@ -18,9 +18,10 @@ struct sof;
 
 #define CLK_CPU(x)				(x)
 #define CLK_DEFAULT_CPU_HZ			26000000
-#define CLK_MAX_CPU_HZ				800000000
+/* check vcore voltage before select higher frequency than 300M */
+#define CLK_MAX_CPU_HZ				300000000
 #define NUM_CLOCKS				1
-#define NUM_CPU_FREQ				5
+#define NUM_CPU_FREQ				3
 
 /* MTK_ADSP_CLK_BUS_UPDATE */
 #define MTK_ADSP_CLK_BUS_UPDATE_BIT		BIT(31)
@@ -29,10 +30,8 @@ struct sof;
 #define MTK_ADSP_CLK_BUS_SRC_EMI		0
 #define MTK_ADSP_CLK_BUS_SRC_LOCAL		1
 
-/* MTK_CLK_CFG_UPDATE */
-#define MTK_CLK_CFG_ADSP_UPDATE			BIT(16)
-
 /* MTK_CLK_CFG_11 */
+#define MTK_CLK_CFG_ADSP_UPDATE			BIT(16)
 #define MTK_CLK_ADSP_OFFSET			24
 #define MTK_CLK_ADSP_MASK			0x7
 #define MTK_CLK_ADSP_26M			0
@@ -42,14 +41,31 @@ struct sof;
 #define MTK_CLK_ADSP_DSPPLL_4			4
 #define MTK_CLK_ADSP_DSPPLL_8			5
 
+/* MTK_CLK_CFG_15 */
+#define MTK_CLK_CFG_ADSP_BUS_UPDATE		BIT(31)
+#define MTK_CLK_ADSP_BUS_OFFSET			17
+#define MTK_CLK_ADSP_BUS_MASK			0x7
+#define MTK_CLK_ADSP_BUS_26M			0
+#define MTK_CLK_ADSP_BUS_ULPOSC_D_2		1
+#define MTK_CLK_ADSP_BUS_MAINPPLL_D_5		2
+#define MTK_CLK_ADSP_BUS_MAINPPLL_D_2_D_2	3
+#define MTK_CLK_ADSP_BUS_MAINPPLL_D_3		4
+#define MTK_CLK_ADSP_BUS_RESERVED		5
+#define MTK_CLK_ADSP_BUS_UNIVPLL_D_3		6
+
+#define MTK_PLL_BASE_EN				BIT(0)
+#define MTK_PLL_PWR_ON				BIT(0)
+#define MTK_PLL_ISO_EN				BIT(1)
+
+#define MTK_PLL_DIV_RATIO_300M			0x831713B2
+#define MTK_PLL_DIV_RATIO_400M			0x831EC4ED
+
 /* List resource from low to high request */
 /* 0 is the lowest request */
 enum ADSP_HW_DSP_CLK {
 	ADSP_CLK_26M = 0,
-	ADSP_CLK_PLL_800M_D_8,
-	ADSP_CLK_PLL_800M_D_4,
-	ADSP_CLK_PLL_800M_D_2,
-	ADSP_CLK_PLL_800M,
+	ADSP_CLK_PLL_300M,
+	ADSP_CLK_PLL_400M,
 };
 
 void platform_clock_init(struct sof *sof);

src/platform/mt8186/lib/clk.c

@@ -13,6 +13,7 @@
 #include <sof/lib/memory.h>
 #include <sof/lib/notifier.h>
 #include <sof/lib/uuid.h>
+#include <sof/lib/wait.h>
 #include <sof/sof.h>
 #include <sof/spinlock.h>
 #include <sof/trace/trace.h>
@@ -26,17 +27,50 @@ DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_uuid), LOG_LEVEL_INFO);
 /* default voltage is 0.8V */
 const struct freq_table platform_cpu_freq[] = {
 	{  26000000, 26000},
-	{ 100000000, 26000},
-	{ 200000000, 26000},
+	{ 300000000, 26000},
 	{ 400000000, 26000},
-	{ 800000000, 26000},
 };
 
 STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ,
 	      invalid_number_of_cpu_frequencies);
 
 static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS];
 
+static void clk_dsppll_enable(uint32_t value)
+{
+	tr_dbg(&clkdrv_tr, "clk_dsppll_enable: %d\n", value);
+
+	switch (value) {
+	case ADSP_CLK_PLL_300M:
+		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_300M);
+		break;
+	case ADSP_CLK_PLL_400M:
+		io_reg_write(MTK_ADSPPLL_CON1, MTK_PLL_DIV_RATIO_400M);
+		break;
+	default:
+		tr_err(&clkdrv_tr, "invalid dsppll: %d\n", value);
+		return;
+	}
+
+	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, MTK_PLL_PWR_ON);
+	wait_delay_us(20);
+	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, 0);
+	wait_delay_us(1);
+	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_BASE_EN, MTK_PLL_BASE_EN);
+	wait_delay_us(20);
+}
+
+static void clk_dsppll_disable(void)
+{
+	tr_dbg(&clkdrv_tr, "clk_dsppll_disable\n");
+
+	io_reg_update_bits(MTK_ADSPPLL_CON0, MTK_PLL_BASE_EN, 0);
+	wait_delay_us(1);
+	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_ISO_EN, MTK_PLL_ISO_EN);
+	wait_delay_us(1);
+	io_reg_update_bits(MTK_ADSPPLL_CON3, MTK_PLL_PWR_ON, 0);
+}
+
 static void set_mux_adsp_sel(uint32_t value)
 {
 	io_reg_write(MTK_CLK_CFG_11_CLR, MTK_CLK_ADSP_MASK << MTK_CLK_ADSP_OFFSET);
@@ -51,31 +85,48 @@ static void set_mux_adsp_bus_src_sel(uint32_t value)
 {
 	io_reg_write(MTK_ADSP_BUS_SRC, value);
 	io_reg_write(MTK_ADSP_CLK_BUS_UPDATE, MTK_ADSP_CLK_BUS_UPDATE_BIT);
+	wait_delay_us(1);
 
 	tr_dbg(&clkdrv_tr, "adsp_bus_mux=%x, MTK_ADSP_BUS_SRC=0x%08x\n",
 	       value, io_reg_read(MTK_ADSP_BUS_SRC));
 }
 
+static void set_mux_adsp_bus_sel(uint32_t value)
+{
+	io_reg_write(MTK_CLK_CFG_15_CLR, MTK_CLK_ADSP_BUS_MASK << MTK_CLK_ADSP_BUS_OFFSET);
+	io_reg_write(MTK_CLK_CFG_15_SET, value << MTK_CLK_ADSP_BUS_OFFSET);
+	io_reg_write(MTK_CLK_CFG_UPDATE, MTK_CLK_CFG_ADSP_BUS_UPDATE);
+
+	tr_dbg(&clkdrv_tr, "adsp_bus_clk_mux=%x, CLK_CFG_15=0x%08x\n",
+	       value, io_reg_read(MTK_CLK_CFG_15));
+}
+
 static int clock_platform_set_dsp_freq(int clock, int freq_idx)
 {
 	switch (freq_idx) {
 	case ADSP_CLK_26M:
+		set_mux_adsp_bus_sel(MTK_CLK_ADSP_BUS_26M);
+		set_mux_adsp_bus_src_sel(MTK_ADSP_CLK_BUS_SRC_LOCAL);
 		set_mux_adsp_sel(MTK_CLK_ADSP_26M);
+		clk_dsppll_disable();
 		break;
-	case ADSP_CLK_PLL_800M_D_8:
-		set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_8);
-		break;
-	case ADSP_CLK_PLL_800M_D_4:
-		set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_4);
-		break;
-	case ADSP_CLK_PLL_800M_D_2:
-		set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL_2);
+	case ADSP_CLK_PLL_300M:
+		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
+		clk_dsppll_enable(ADSP_CLK_PLL_300M);
+		set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
+		set_mux_adsp_bus_src_sel(MTK_ADSP_CLK_BUS_SRC_EMI);
+		set_mux_adsp_bus_sel(MTK_CLK_ADSP_BUS_26M);
 		break;
-	case ADSP_CLK_PLL_800M:
+	case ADSP_CLK_PLL_400M:
+		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
+		clk_dsppll_enable(ADSP_CLK_PLL_400M);
 		set_mux_adsp_sel(MTK_CLK_ADSP_DSPPLL);
+		set_mux_adsp_bus_src_sel(MTK_ADSP_CLK_BUS_SRC_EMI);
+		set_mux_adsp_bus_sel(MTK_CLK_ADSP_BUS_26M);
 		break;
 	default:
-		set_mux_adsp_sel(MTK_CLK_ADSP_26M);
+		clock_platform_set_dsp_freq(clock, ADSP_CLK_26M);
+		tr_err(&clkdrv_tr, "unknown freq index %x\n", freq_idx);
 		break;
 	}
 
@@ -102,6 +153,5 @@ void platform_clock_init(struct sof *sof)
 		k_spinlock_init(&sof->clocks[i].lock);
 	}
 
-	/* DSP bus clock */
-	set_mux_adsp_bus_src_sel(MTK_ADSP_CLK_BUS_SRC_EMI);
+	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
 }

src/platform/mt8186/platform.c

@@ -153,12 +153,6 @@ int platform_boot_complete(uint32_t boot_message)
 	/* now interrupt host to tell it we are done booting */
 	trigger_irq_to_host_req();
 
-	/* boot now complete so we can relax the CPU */
-	/* For now skip this to gain more processing performance
-	 * for SRC component.
-	 */
-	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_MAX_CPU_HZ);
-
 	return 0;
 }
 
@@ -214,5 +208,6 @@ int platform_init(struct sof *sof)
 
 int platform_context_save(struct sof *sof)
 {
+	clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ);
 	return 0;
 }

tools/topology/topology1/CMakeLists.txt

@@ -236,8 +236,8 @@ set(TPLGS
         "sof-mt8195-mt6359-rt1019-rt5682\;sof-mt8195-mt6359-max98390-rt5682"
 	"sof-mt8195-mt6359-rt1019-rt5682\;sof-mt8195-mt6359-max98390-rt5682-rtnr\;-DCHANNELS=2\;-DRTNR"
 	"sof-mt8195-mt6359-rt1019-rt5682\;sof-mt8195-mt6359-max98390-rt5682-google-aec-rtnr\;-DGOOGLE_RTC_AUDIO_PROCESSING\;-DCHANNELS=2\;-DRTNR"
-	"sof-mt8186-mt6366\;sof-mt8186-mt6366-rt1019-rt5682s"
-	"sof-mt8186-mt6366\;sof-mt8186-mt6366-da7219-max98357"
+	"sof-mt8186-mt6366\;sof-mt8186"
+	"sof-mt8186-mt6366\;sof-mt8186-mt6366-rt1019-rt5682s-waves\;-DWAVES=1"
 
 	"sof-acp-renoir\;sof-acp"
 	"sof-rn-rt5682-rt1019\;sof-rn-rt5682-rt1019"