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Cdns torrent phy regmap v2 #46

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Cdns torrent phy regmap v2 #46

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34bdd72
phy: phy-cadence-torrent: Use regmap to read and write Torrent PHY re…
sjakhadecdns Nov 1, 2019
2ad948c
phy: phy-cadence-torrent: Use regmap to read and write DPTX PHY regis…
sjakhadecdns Nov 1, 2019
ad5f5a3
dt-bindings: phy: phy-cadence-torrent: Add platform dependent compati…
sjakhadecdns Nov 1, 2019
6e645d9
phy: phy-cadence-torrent: Add platform dependent initialization struc…
sjakhadecdns Nov 1, 2019
4f2d9dc
arm64: dts: ti: k3-j721e-main: Update Cadence Torrent PHY compatible …
sjakhadecdns Nov 1, 2019
2e09ab6
phy: ti: j721e-wiz: Update Cadence Torrent PHY compatible string
sjakhadecdns Nov 1, 2019
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1 change: 1 addition & 0 deletions Documentation/devicetree/bindings/phy/phy-cadence-torrent.txt
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Expand Up @@ -7,6 +7,7 @@ the Cadence MHDP DisplayPort controller.
-------------------------------------------------------------------------------
Required properties (controller (parent) node):
- compatible : Should be "cdns,torrent-phy"
Use "ti,j721e-serdes-10g" for TI J7 SoCs
- clocks : PHY reference clock. Must contain an entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names : Must be "refclk"
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2 changes: 1 addition & 1 deletion arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
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Expand Up @@ -928,7 +928,7 @@

serdes4: serdes@5050000 {
/* XXX we also map EDP0 registers here as the PHY driver needs those... */
compatible = "cdns,torrent-phy";
compatible = "ti,j721e-serdes-10g";
reg = <0x00 0x05050000 0x0 0x00010000>, /* SERDES_10G0 */
<0x00 0x0A030A00 0x0 0x00000040>; /* DSS_EDP0_V2A_CORE_VP_REGS_APB + 30A00 */

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