v1.10.7

What's Changed

• ⚠️ Relocate VUnit testbench to another sub-repository (neorv32-vunit) by @stnolting in #1083
• [github workflow] remove packages by @stnolting in #1085
• 🧪 convert VHDL memory images into full-scale VHDL packages by @stnolting in #1084
• ⚠️ Rework processor boot configuration by @stnolting in #1086
• Minor rtl edits and cleanups by @stnolting in #1090
• Rework default testbench by @stnolting in #1093
• 🧪 Use xpack risc-v gcc as default prebuilt toolchain by @stnolting in #1091
• [CPU control] large code cleanup by @stnolting in #1099
• Fixed typo and cpu_alu architecture renaming for consistency by @LukasP46 in #1102
• [docs/makefile] Copy figures also for single targets by @LukasP46 in #1101
• [rtl] fix some Verilog [sic] issues by @stnolting in #1103
• [sw] Use build folder and add example for more complex project structure by @LukasP46 in #1107
• [TWI] add bus sensing logic by @stnolting in #1111
• [sw] Add UART disable tag by @LukasP46 in #1112
• ✨ add ONEWIRE command FIFO; 🐛 fix ONEWIRE status flag by @stnolting in #1113
• use vhdl 2008 standard in ghdl simulations by @csantosb in #1096
• [docs] Fix missing " in makefile by @LukasP46 in #1117

New Contributors

• @LukasP46 made their first contribution in #1102
• @csantosb made their first contribution in #1096

Full Changelog: v1.10.6...v1.10.7