Rtc

examples/rtc.rs

@@ -0,0 +1,47 @@
+#![no_main]
+#![no_std]
+
+use hal::{
+    delay::SYSTDelayExt,
+    rcc::RccExt,
+    rtc::RtcExt,
+    stm32::Peripherals,
+    time::{Date, ExtU32, Month, MonthDay, Time, Year},
+};
+use stm32g4xx_hal as hal;
+
+use cortex_m_rt::entry;
+
+use utils::logger::info;
+
+#[macro_use]
+mod utils;
+
+#[entry]
+fn main() -> ! {
+    utils::logger::init();
+
+    info!("start");
+
+    let dp = Peripherals::take().unwrap();
+    let cp = cortex_m::Peripherals::take().expect("cannot take core peripherals");
+
+    info!("rcc");
+
+    let mut rcc = dp.RCC.constrain();
+
+    info!("Setup rtc");
+    let mut delay = cp.SYST.delay(&rcc.clocks);
+    let mut rtc = dp.RTC.constrain(&mut rcc);
+
+    info!("Setup date");
+    rtc.set_date(&Date::new(Year(2024), Month(8), MonthDay(5)));
+    rtc.set_time(&Time::new(0.hours(), 59.minutes(), 2.secs(), true));
+
+    info!("Enter Loop");
+
+    loop {
+        info!("Timestamp: {:?} {:?}", rtc.get_date(), rtc.get_time());
+        delay.delay_ms(500);
+    }
+}

src/lib.rs

@@ -88,6 +88,7 @@ pub mod pwm;
 pub mod pwr;
 // pub mod qei;
 pub mod rcc;
+pub mod rtc;
 // pub mod rng;
 pub mod serial;
 pub mod signature;

src/rcc/config.rs

@@ -46,6 +46,16 @@ pub enum PLLSrc {
     HSE_BYPASS(Hertz),
 }
 
+/// RTC clock input source
+#[derive(Clone, Copy)]
+pub enum RtcSrc {
+    LSE,
+    LSE_BYPASS,
+    LSI,
+    HSE,
+    HSE_BYPASS,
+}
+
 /// Divider for the PLL clock input (M)
 /// This must be set based on the input clock to keep the PLL input frequency within the limits
 /// specified in the datasheet.

src/rcc/mod.rs

@@ -231,12 +231,6 @@ impl Rcc {
         }
     }
 
-    pub fn unlock_rtc(&mut self) {
-        self.rb.apb1enr1.modify(|_, w| w.pwren().set_bit());
-        let pwr = unsafe { &(*PWR::ptr()) };
-        pwr.cr1.modify(|_, w| w.dbp().set_bit());
-    }
-
     fn config_pll(&self, pll_cfg: PllConfig) -> PLLClocks {
         // Disable PLL
         self.rb.cr.modify(|_, w| w.pllon().clear_bit());
@@ -457,6 +451,46 @@ impl Rcc {
     pub fn clear_reset_reason(&mut self) {
         self.rb.csr.modify(|_, w| w.rmvf().set_bit());
     }
+
+    pub(crate) fn unlock_rtc(&self) {
+        self.rb.apb1enr1.modify(|_, w| w.pwren().set_bit());
+        let pwr = unsafe { &(*PWR::ptr()) };
+        pwr.cr1.modify(|_, w| w.dbp().set_bit());
+        while pwr.cr1.read().dbp().bit_is_clear() {}
+    }
+
+    pub(crate) fn enable_rtc(&self, src: RtcSrc) {
+        self.unlock_rtc();
+        self.rb
+            .apb1enr1
+            .modify(|_, w| w.rtcapben().set_bit().pwren().set_bit());
+        self.rb.apb1smenr1.modify(|_, w| w.rtcapbsmen().set_bit());
+        self.rb.bdcr.modify(|_, w| w.bdrst().set_bit());
+
+        let rtc_sel = match src {
+            RtcSrc::LSE | RtcSrc::LSE_BYPASS => 0b01,
+            RtcSrc::LSI => 0b10,
+            RtcSrc::HSE | RtcSrc::HSE_BYPASS => 0b11,
+        };
+
+        self.rb.bdcr.modify(|_, w| {
+            w.rtcsel()
+                .bits(rtc_sel)
+                .rtcen()
+                .set_bit()
+                .bdrst()
+                .clear_bit()
+        });
+
+        self.unlock_rtc();
+        match src {
+            RtcSrc::LSE => self.enable_lse(false),
+            RtcSrc::LSE_BYPASS => self.enable_lse(true),
+            RtcSrc::LSI => self.enable_lsi(),
+            RtcSrc::HSE => self.enable_hse(false),
+            RtcSrc::HSE_BYPASS => self.enable_hse(true),
+        };
+    }
 }
 
 pub struct ResetReason {