Update to pac changes

stm32-rs · Nov 18, 2024 · fd92940 · fd92940
1 parent b524806
commit fd92940
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/src/hrtim/capture.rs b/src/hrtim/capture.rs
@@ -224,7 +224,7 @@ macro_rules! impl_capture {
                 let tim = unsafe { &*$TIMX::ptr() };
 
                 // No need for exclusive access since this is a write only register
-                tim.icr().write(|w| w.$cptXc().bit(true));
+                tim.icr().write(|w| w.$cptXc().clear());
             }
 
             fn is_pending(&self) -> bool {

diff --git a/src/hrtim/fault.rs b/src/hrtim/fault.rs
@@ -152,7 +152,7 @@ impl_faults!(
     FaultInput3 => FaultSource3: PINS=[(PB10, AF13)], COMP=COMP6, 0b000100, fltinr1, flt3src, flt3src_1, flt3p, flt3f, flt3e, flt3lck,
     FaultInput4 => FaultSource4: PINS=[(PB11, AF13)], COMP=COMP1, 0b001000, fltinr1, flt4src, flt4src_1, flt4p, flt4f, flt4e, flt4lck,
     FaultInput5 => FaultSource5: PINS=[(PB0, AF13), (PC7, AF3)], COMP=COMP3, 0b010000, fltinr2, flt5src, flt5src_1, flt5p, flt5f, flt5e, flt5lck,
-    FaultInput6 => FaultSource6: PINS=[(PC10, AF13)], COMP=COMP5, 0b100000, fltinr2, flt6src_0, flt6src_1, flt6p, flt6f, flt6e, flt6lck,
+    FaultInput6 => FaultSource6: PINS=[(PC10, AF13)], COMP=COMP5, 0b100000, fltinr2, flt6src, flt6src_1, flt6p, flt6f, flt6e, flt6lck,
 );
 
 pub struct FaultInputs {
@@ -253,7 +253,7 @@ macro_rules! impl_flt_monitor {
 
             fn clear_fault(&mut self) {
                 let common = unsafe { &*HRTIM_COMMON::ptr() };
-                common.icr().write(|w| w.$fltxc().set_bit());
+                common.icr().write(|w| w.$fltxc().clear());
             }
         }
     )+};
@@ -267,4 +267,4 @@ impl_flt_monitor!(
     FltMonitor4: (flt4, flt4c, flt4ie),
     FltMonitor5: (flt5, flt5c, flt5ie),
     FltMonitor6: (flt6, flt6c, flt6ie),
-);
+);
diff --git a/src/hrtim/timer.rs b/src/hrtim/timer.rs
@@ -170,7 +170,7 @@ macro_rules! hrtim_timer {
             fn clear_repetition_interrupt(&mut self) {
                 let tim = unsafe { &*$TIMX::ptr() };
 
-                tim.icr().write(|w| w.repc().bit(true));
+                tim.icr().write(|w| w.repc().clear());
             }
 
             /// Disable register updates
@@ -352,4 +352,4 @@ impl<DST, PSCL, CPT1, CPT2> super::event::EventSource<DST, PSCL>
     for HrTim<HRTIM_MASTER, PSCL, CPT1, CPT2>
 {
     const BITS: u32 = 1 << 7; // MSTPER
-}
+}