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Update for new pac changes
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@usbalbin
usbalbin committed Nov 16, 2024
1 parent 0a893cc commit 469b993
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Showing 7 changed files with 205 additions and 225 deletions.
3 changes: 2 additions & 1 deletion Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,8 @@ version = "0.0.2"
[dependencies]
nb = "0.1.1"
#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
stm32g4 = { version = "0.17.0", package = "stm32g4-staging" }
#stm32g4 = { version = "0.18.0", package = "stm32g4-staging" }
stm32g4 = { path = "../stm32-rs/stm32g4" }
paste = "1.0"
bitflags = "1.2"
vcell = "0.1"
Expand Down
52 changes: 23 additions & 29 deletions src/hrtim/capture.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -149,7 +149,12 @@ pub fn dma_value_to_signed(x: u32, period: u16) -> i32 {
}

macro_rules! impl_capture {
($($TIMX:ident: $CH:ident, $cptXYr:ident, $cptXYcr:ident, $cptXx:ident, $dier:ident, $icr:ident, $isr:ident, $cptXie:ident, $cptXde:ident, $cptXc:ident, $cptX:ident, $mux:expr),+) => {$(
($($TIMX:ident: $mux:expr),+) => {$(
impl_capture!($TIMX: Ch1, cpt1r, cpt1cr, cpt1, cpt1ie, cpt1de, cpt1c, $mux);
impl_capture!($TIMX: Ch2, cpt2r, cpt2cr, cpt2, cpt2ie, cpt2de, cpt2c, $mux);
)+};

($TIMX:ident: $CH:ident, $cptXr:ident, $cptXcr:ident, $cptX:ident, $cptXie:ident, $cptXde:ident, $cptXc:ident, $mux:expr) => {
impl<PSCL> HrCapt<$TIMX, PSCL, $CH, NoDma> {
/// Add event to capture
///
Expand All @@ -160,7 +165,7 @@ macro_rules! impl_capture {

// SAFETY: We are the only one with access to cptXYcr
unsafe {
tim.$cptXYcr().modify(|r, w| w.bits(r.bits() | E::BITS));
tim.$cptXcr().modify(|r, w| w.bits(r.bits() | E::BITS));
}
}

Expand All @@ -170,7 +175,7 @@ macro_rules! impl_capture {

// SAFETY: We are the only one with access to cptXYcr
unsafe {
tim.$cptXYcr().modify(|r, w| w.bits(r.bits() & !E::BITS));
tim.$cptXcr().modify(|r, w| w.bits(r.bits() & !E::BITS));
}
}

Expand All @@ -179,7 +184,7 @@ macro_rules! impl_capture {
// SAFETY: We are the only one with access to cptXYcr
let tim = unsafe { &*$TIMX::ptr() };

tim.$cptXYcr().modify(|_, w| w.swcpt().set_bit());
tim.$cptXcr().modify(|_, w| w.swcpt().set_bit());
}

// TODO: It would be sufficient to instead of hr_control only require exclusive access to the owning timer
Expand All @@ -188,13 +193,13 @@ macro_rules! impl_capture {
pub fn enable_interrupt(&mut self, enable: bool, _hr_control: &mut super::HrPwmControl) {
let tim = unsafe { &*$TIMX::ptr() };

tim.$dier().modify(|_r, w| w.$cptXie().bit(enable));
tim.dier().modify(|_r, w| w.$cptXie().bit(enable));
}

pub fn enable_dma(self, _ch: timer::DmaChannel<$TIMX>) -> HrCapt<$TIMX, PSCL, $CH, Dma> {
// SAFETY: We own the only insance of this timers dma channel, no one else can do this
let tim = unsafe { &*$TIMX::ptr() };
tim.$dier().modify(|_r, w| w.$cptXde().set_bit());
tim.dier().modify(|_r, w| w.$cptXde().set_bit());
HrCapt {
_x: PhantomData
}
Expand All @@ -204,13 +209,13 @@ macro_rules! impl_capture {
impl<PSCL, DMA> HrCapture for HrCapt<$TIMX, PSCL, $CH, DMA> {
fn get_last(&self) -> (u16, CountingDirection) {
let tim = unsafe { &*$TIMX::ptr() };
let data = tim.$cptXYr().read();
let data = tim.$cptXr().read();

let dir = match data.dir().bit() {
true => CountingDirection::Down,
false => CountingDirection::Up,
};
let value = data.$cptXx().bits();
let value = data.cpt().bits();

(value, dir)
}
Expand All @@ -219,47 +224,36 @@ macro_rules! impl_capture {
let tim = unsafe { &*$TIMX::ptr() };

// No need for exclusive access since this is a write only register
tim.$icr().write(|w| w.$cptXc().set_bit());
tim.icr().write(|w| w.$cptXc().bit(true));
}

fn is_pending(&self) -> bool {
let tim = unsafe { &*$TIMX::ptr() };

// No need for exclusive access since this is a read only register
tim.$isr().read().$cptX().bit()
tim.isr().read().$cptX().bit()
}
}

unsafe impl<PSCL> TargetAddress<PeripheralToMemory> for HrCapt<$TIMX, PSCL, $CH, Dma> {
#[inline(always)]
fn address(&self) -> u32 {
let tim = unsafe { &*$TIMX::ptr() };
&tim.$cptXYr() as *const _ as u32
&tim.$cptXr() as *const _ as u32
}

type MemSize = u32;

const REQUEST_LINE: Option<u8> = Some($mux as u8);
}
)+};
};
}

impl_capture! {
HRTIM_TIMA: Ch1, cpt1ar, cpt1acr, cpt1x, timadier, timaicr, timaisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMA,
HRTIM_TIMA: Ch2, cpt2ar, cpt2acr, cpt2x, timadier, timaicr, timaisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMA,

HRTIM_TIMB: Ch1, cpt1br, cpt1bcr, cpt1x, timbdier, timbicr, timbisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMB,
HRTIM_TIMB: Ch2, cpt2br, cpt2bcr, cpt2x, timbdier, timbicr, timbisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMB,

HRTIM_TIMC: Ch1, cpt1cr, cpt1ccr, cpt1x, timcdier, timcicr, timcisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMC,
HRTIM_TIMC: Ch2, cpt2cr, cpt2ccr, cpt2x, timcdier, timcicr, timcisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMC,

HRTIM_TIMD: Ch1, cpt1dr, cpt1dcr, cpt1x, timddier, timdicr, timdisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMD,
HRTIM_TIMD: Ch2, cpt2dr, cpt2dcr, cpt2x, timddier, timdicr, timdisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMD,

HRTIM_TIME: Ch1, cpt1er, cpt1ecr, cpt1x, timedier, timeicr, timeisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIME,
HRTIM_TIME: Ch2, cpt2er, cpt2ecr, cpt2x, timedier, timeicr, timeisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIME,

HRTIM_TIMF: Ch1, cpt1fr, cpt1fcr, cpt1x, timfdier, timficr, timfisr, cpt1ie, cpt1de, cpt1c, cpt1, DmaMuxResources::HRTIM_TIMF,
HRTIM_TIMF: Ch2, cpt2fr, cpt2fcr, cpt2x, timfdier, timficr, timfisr, cpt2ie, cpt2de, cpt2c, cpt2, DmaMuxResources::HRTIM_TIMF
HRTIM_TIMA: DmaMuxResources::HRTIM_TIMA,
HRTIM_TIMB: DmaMuxResources::HRTIM_TIMB,
HRTIM_TIMC: DmaMuxResources::HRTIM_TIMC,
HRTIM_TIMD: DmaMuxResources::HRTIM_TIMD,
HRTIM_TIME: DmaMuxResources::HRTIM_TIME,
HRTIM_TIMF: DmaMuxResources::HRTIM_TIMF
}
82 changes: 41 additions & 41 deletions src/hrtim/compare_register.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -21,17 +21,17 @@ use super::adc_trigger::Adc6810Trigger as Adc6810;

macro_rules! hrtim_cr_helper {
(HRTIM_MASTER: $cr_type:ident:
$cmpXYr:ident, $cmpYx:ident,
$cmpXYr:ident,
[$(($Trigger:ty: $trigger_bits:expr)),*],
[$(($event_dst:ident, $tim_event_index:expr)),*],
$bit_index:literal
) => {
// Strip bit_index since master timer has other bits that are common across all destinations
hrtim_cr_helper!(HRTIM_MASTER: $cr_type: $cmpXYr, $cmpYx, [$(($Trigger: $trigger_bits)),*], [$(($event_dst, $tim_event_index)),*]);
hrtim_cr_helper!(HRTIM_MASTER: $cr_type: $cmpXYr, [$(($Trigger: $trigger_bits)),*], [$(($event_dst, $tim_event_index)),*]);
};

($TIMX:ident: $cr_type:ident:
$cmpXYr:ident, $cmpYx:ident,
$cmpXYr:ident,
[$(($Trigger:ty: $trigger_bits:expr)),*],
[$(($event_dst:ident, $tim_event_index:expr)),*]
$(, $bit_index:literal)*
Expand All @@ -40,12 +40,12 @@ macro_rules! hrtim_cr_helper {
fn get_duty(&self) -> u16 {
let tim = unsafe { &*$TIMX::ptr() };

tim.$cmpXYr().read().$cmpYx().bits()
tim.$cmpXYr().read().cmp().bits()
}
fn set_duty(&mut self, duty: u16) {
let tim = unsafe { &*$TIMX::ptr() };

tim.$cmpXYr().write(|w| unsafe { w.$cmpYx().bits(duty) });
tim.$cmpXYr().write(|w| unsafe { w.cmp().bits(duty) });
}
}

Expand Down Expand Up @@ -73,67 +73,67 @@ macro_rules! hrtim_cr_helper {

macro_rules! hrtim_cr {
($($TIMX:ident: [
[$cmpX1r:ident, $cmp1x:ident, [$(($cr1_trigger:ident: $cr1_trigger_bits:expr)),*], [$(($cr1_event_dst:ident, $cr1_tim_event_index:expr)),*]],
[$cmpX2r:ident, $cmp2x:ident, [$(($cr2_trigger:ident: $cr2_trigger_bits:expr)),*], [$(($cr2_event_dst:ident, $cr2_tim_event_index:expr)),*]],
[$cmpX3r:ident, $cmp3x:ident, [$(($cr3_trigger:ident: $cr3_trigger_bits:expr)),*], [$(($cr3_event_dst:ident, $cr3_tim_event_index:expr)),*]],
[$cmpX4r:ident, $cmp4x:ident, [$(($cr4_trigger:ident: $cr4_trigger_bits:expr)),*], [$(($cr4_event_dst:ident, $cr4_tim_event_index:expr)),*]]
[$(($cr1_trigger:ident: $cr1_trigger_bits:expr)),*], [$(($cr1_event_dst:ident, $cr1_tim_event_index:expr)),*],
[$(($cr2_trigger:ident: $cr2_trigger_bits:expr)),*], [$(($cr2_event_dst:ident, $cr2_tim_event_index:expr)),*],
[$(($cr3_trigger:ident: $cr3_trigger_bits:expr)),*], [$(($cr3_event_dst:ident, $cr3_tim_event_index:expr)),*],
[$(($cr4_trigger:ident: $cr4_trigger_bits:expr)),*], [$(($cr4_event_dst:ident, $cr4_tim_event_index:expr)),*]
]),+) => {$(
hrtim_cr_helper!($TIMX: HrCr1: $cmpX1r, $cmp1x, [$(($cr1_trigger: $cr1_trigger_bits)),*], [$(($cr1_event_dst, $cr1_tim_event_index)),*], 3);
hrtim_cr_helper!($TIMX: HrCr2: $cmpX2r, $cmp2x, [$(($cr2_trigger: $cr2_trigger_bits)),*], [$(($cr2_event_dst, $cr2_tim_event_index)),*], 4);
hrtim_cr_helper!($TIMX: HrCr3: $cmpX3r, $cmp3x, [$(($cr3_trigger: $cr3_trigger_bits)),*], [$(($cr3_event_dst, $cr3_tim_event_index)),*], 5);
hrtim_cr_helper!($TIMX: HrCr4: $cmpX4r, $cmp4x, [$(($cr4_trigger: $cr4_trigger_bits)),*], [$(($cr4_event_dst, $cr4_tim_event_index)),*], 6);
hrtim_cr_helper!($TIMX: HrCr1: cmp1r, [$(($cr1_trigger: $cr1_trigger_bits)),*], [$(($cr1_event_dst, $cr1_tim_event_index)),*], 3);
hrtim_cr_helper!($TIMX: HrCr2: cmp2r, [$(($cr2_trigger: $cr2_trigger_bits)),*], [$(($cr2_event_dst, $cr2_tim_event_index)),*], 4);
hrtim_cr_helper!($TIMX: HrCr3: cmp3r, [$(($cr3_trigger: $cr3_trigger_bits)),*], [$(($cr3_event_dst, $cr3_tim_event_index)),*], 5);
hrtim_cr_helper!($TIMX: HrCr4: cmp4r, [$(($cr4_trigger: $cr4_trigger_bits)),*], [$(($cr4_event_dst, $cr4_tim_event_index)),*], 6);
)+};
}

// See RM0440 Table 218. 'Events mapping across timer A to F'
hrtim_cr! {
HRTIM_MASTER: [
[mcmp1r, mcmp1, [(Adc13: 1 << 0), (Adc24: 1 << 0), (Adc579: 0), (Adc6810: 0) ], []],
[mcmp2r, mcmp2, [(Adc13: 1 << 1), (Adc24: 1 << 1), (Adc579: 1), (Adc6810: 1) ], []],
[mcmp3r, mcmp3, [(Adc13: 1 << 2), (Adc24: 1 << 2), (Adc579: 2), (Adc6810: 2) ], []],
[mcmp4r, mcmp4, [(Adc13: 1 << 3), (Adc24: 1 << 3), (Adc579: 3), (Adc6810: 3) ], []]
[(Adc13: 1 << 0), (Adc24: 1 << 0), (Adc579: 0), (Adc6810: 0) ], [],
[(Adc13: 1 << 1), (Adc24: 1 << 1), (Adc579: 1), (Adc6810: 1) ], [],
[(Adc13: 1 << 2), (Adc24: 1 << 2), (Adc579: 2), (Adc6810: 2) ], [],
[(Adc13: 1 << 3), (Adc24: 1 << 3), (Adc579: 3), (Adc6810: 3) ], []
],

HRTIM_TIMA: [
[cmp1ar, cmp1x, [ ], [(HRTIM_TIMB, 1), (HRTIM_TIMD, 1) ]],
[cmp2ar, cmp2x, [ (Adc24: 1 << 10), (Adc6810: 10)], [(HRTIM_TIMB, 2), (HRTIM_TIMC, 1) ]],
[cmp3ar, cmp3x, [(Adc13: 1 << 11), (Adc579: 10) ], [(HRTIM_TIMC, 2), (HRTIM_TIMF, 1) ]],
[cmp4ar, cmp4x, [(Adc13: 1 << 12), (Adc24: 1 << 12), (Adc579: 11), (Adc6810: 11)], [(HRTIM_TIMD, 2), (HRTIM_TIME, 1) ]]
[ ], [(HRTIM_TIMB, 1), (HRTIM_TIMD, 1) ],
[ (Adc24: 1 << 10), (Adc6810: 10)], [(HRTIM_TIMB, 2), (HRTIM_TIMC, 1) ],
[(Adc13: 1 << 11), (Adc579: 10) ], [(HRTIM_TIMC, 2), (HRTIM_TIMF, 1) ],
[(Adc13: 1 << 12), (Adc24: 1 << 12), (Adc579: 11), (Adc6810: 11)], [(HRTIM_TIMD, 2), (HRTIM_TIME, 1) ]
],

HRTIM_TIMB: [
[cmp1br, cmp1x, [ ], [(HRTIM_TIMA, 1), (HRTIM_TIMF, 2) ]],
[cmp2br, cmp2x, [ (Adc24: 1 << 14), (Adc6810: 13)], [(HRTIM_TIMA, 2), (HRTIM_TIMC, 3), (HRTIM_TIMD, 3)]],
[cmp3br, cmp3x, [(Adc13: 1 << 16), (Adc579: 14) ], [(HRTIM_TIMC, 4), (HRTIM_TIME, 2) ]],
[cmp4br, cmp4x, [(Adc13: 1 << 17), (Adc24: 1 << 16), (Adc579: 15), (Adc6810: 14)], [(HRTIM_TIMD, 4), (HRTIM_TIME, 3), (HRTIM_TIMF, 3)]]
[ ], [(HRTIM_TIMA, 1), (HRTIM_TIMF, 2) ],
[ (Adc24: 1 << 14), (Adc6810: 13)], [(HRTIM_TIMA, 2), (HRTIM_TIMC, 3), (HRTIM_TIMD, 3)],
[(Adc13: 1 << 16), (Adc579: 14) ], [(HRTIM_TIMC, 4), (HRTIM_TIME, 2) ],
[(Adc13: 1 << 17), (Adc24: 1 << 16), (Adc579: 15), (Adc6810: 14)], [(HRTIM_TIMD, 4), (HRTIM_TIME, 3), (HRTIM_TIMF, 3)]
],

HRTIM_TIMC: [
[cmp1cr, cmp1x, [ ], [(HRTIM_TIME, 4), (HRTIM_TIMF, 4) ]],
[cmp2cr, cmp2x, [ (Adc24: 1 << 18), (Adc6810: 16)], [(HRTIM_TIMA, 3), (HRTIM_TIME, 5) ]],
[cmp3cr, cmp3x, [(Adc13: 1 << 21), (Adc579: 18) ], [(HRTIM_TIMA, 4), (HRTIM_TIMB, 3) ]],
[cmp4cr, cmp4x, [(Adc13: 1 << 22), (Adc24: 1 << 20), (Adc579: 19), (Adc6810: 17)], [(HRTIM_TIMB, 4), (HRTIM_TIMD, 5), (HRTIM_TIMF, 5)]]
[ ], [(HRTIM_TIME, 4), (HRTIM_TIMF, 4) ],
[ (Adc24: 1 << 18), (Adc6810: 16)], [(HRTIM_TIMA, 3), (HRTIM_TIME, 5) ],
[(Adc13: 1 << 21), (Adc579: 18) ], [(HRTIM_TIMA, 4), (HRTIM_TIMB, 3) ],
[(Adc13: 1 << 22), (Adc24: 1 << 20), (Adc579: 19), (Adc6810: 17)], [(HRTIM_TIMB, 4), (HRTIM_TIMD, 5), (HRTIM_TIMF, 5)]
],

HRTIM_TIMD: [
[cmp1dr, cmp1x, [ ], [(HRTIM_TIMA, 5), (HRTIM_TIME, 6) ]],
[cmp2dr, cmp2x, [ (Adc24: 1 << 23), (Adc6810: 20)], [(HRTIM_TIMA, 6), (HRTIM_TIMC, 5), (HRTIM_TIME, 7)]],
[cmp3dr, cmp3x, [(Adc13: 1 << 25), (Adc579: 21) ], [(HRTIM_TIMB, 5), (HRTIM_TIMF, 6) ]],
[cmp4dr, cmp4x, [(Adc13: 1 << 26), (Adc24: 1 << 25), (Adc579: 22), (Adc6810: 21)], [(HRTIM_TIMB, 6), (HRTIM_TIMC, 6), (HRTIM_TIMF, 7)]]
[ ], [(HRTIM_TIMA, 5), (HRTIM_TIME, 6) ],
[ (Adc24: 1 << 23), (Adc6810: 20)], [(HRTIM_TIMA, 6), (HRTIM_TIMC, 5), (HRTIM_TIME, 7)],
[(Adc13: 1 << 25), (Adc579: 21) ], [(HRTIM_TIMB, 5), (HRTIM_TIMF, 6) ],
[(Adc13: 1 << 26), (Adc24: 1 << 25), (Adc579: 22), (Adc6810: 21)], [(HRTIM_TIMB, 6), (HRTIM_TIMC, 6), (HRTIM_TIMF, 7)]
],

HRTIM_TIME: [
[cmp1er, cmp1x, [ ], [(HRTIM_TIMB, 7), (HRTIM_TIMD, 6) ]],
[cmp2er, cmp2x, [ (Adc24: 1 << 28), (Adc6810: 24)], [(HRTIM_TIMB, 8), (HRTIM_TIMF, 8) ]],
[cmp3er, cmp3x, [(Adc13: 1 << 29), (Adc24: 1 << 29), (Adc579: 24), (Adc6810: 25)], [(HRTIM_TIMA, 7), (HRTIM_TIMC, 7), (HRTIM_TIMF, 9)]],
[cmp4er, cmp4x, [(Adc13: 1 << 30), (Adc24: 1 << 30), (Adc579: 25), (Adc6810: 26)], [(HRTIM_TIMA, 8), (HRTIM_TIMC, 8), (HRTIM_TIMD, 7)]]
[ ], [(HRTIM_TIMB, 7), (HRTIM_TIMD, 6) ],
[ (Adc24: 1 << 28), (Adc6810: 24)], [(HRTIM_TIMB, 8), (HRTIM_TIMF, 8) ],
[(Adc13: 1 << 29), (Adc24: 1 << 29), (Adc579: 24), (Adc6810: 25)], [(HRTIM_TIMA, 7), (HRTIM_TIMC, 7), (HRTIM_TIMF, 9)],
[(Adc13: 1 << 30), (Adc24: 1 << 30), (Adc579: 25), (Adc6810: 26)], [(HRTIM_TIMA, 8), (HRTIM_TIMC, 8), (HRTIM_TIMD, 7)]
],

HRTIM_TIMF: [
[cmp1fr, cmp1x, [ (Adc24: 1 << 15) ], [(HRTIM_TIMD, 8) ]],
[cmp2fr, cmp2x, [(Adc13: 1 << 10), (Adc24: 1 << 11), (Adc579: 27), (Adc6810: 28)], [(HRTIM_TIMC, 9) ]],
[cmp3fr, cmp3x, [(Adc13: 1 << 15), (Adc579: 28), (Adc6810: 29)], [(HRTIM_TIMB, 9), (HRTIM_TIMD, 9), (HRTIM_TIME, 8)]],
[cmp4fr, cmp4x, [(Adc13: 1 << 20), (Adc24: 1 << 19), (Adc579: 29), (Adc6810: 30)], [(HRTIM_TIMA, 9), (HRTIM_TIME, 9) ]]
[ (Adc24: 1 << 15) ], [(HRTIM_TIMD, 8) ],
[(Adc13: 1 << 10), (Adc24: 1 << 11), (Adc579: 27), (Adc6810: 28)], [(HRTIM_TIMC, 9) ],
[(Adc13: 1 << 15), (Adc579: 28), (Adc6810: 29)], [(HRTIM_TIMB, 9), (HRTIM_TIMD, 9), (HRTIM_TIME, 8)],
[(Adc13: 1 << 20), (Adc24: 1 << 19), (Adc579: 29), (Adc6810: 30)], [(HRTIM_TIMA, 9), (HRTIM_TIME, 9) ]
]
}

Expand Down
2 changes: 1 addition & 1 deletion src/hrtim/fault.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -267,7 +267,7 @@ macro_rules! impl_flt_monitor {
}

impl_flt_monitor!(
FltMonitorSys: (sysflt, sysfltc, sysflte),
FltMonitorSys: (sysflt, sysfltc, sysfltie),
FltMonitor1: (flt1, flt1c, flt1ie),
FltMonitor2: (flt2, flt2c, flt2ie),
FltMonitor3: (flt3, flt3c, flt3ie),
Expand Down
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