make interrupt fire on 10 rather than 11, other fixes

.gitignore

@@ -1,4 +1,5 @@
 .DS_Store
+a.out
 .idea
 *.vcd
 runs

src/byte_transmitter.v

@@ -9,7 +9,7 @@ module byte_transmitter (
     input clk,
     input reset,
     input enable,
-    // TODO: make [31:0] configurable
+    // TODO: make size configurable
     input wire [31:0] in,  // byte_buffer
     output wire out,
     output wire done
@@ -38,7 +38,7 @@ module byte_transmitter (
 `ifdef FORMAL
           f_total_written <= f_total_written + 1;
           assert (r_out != 1'bX);
-          assert (byte_count != 1'bX);
+          assert (byte_count != 5'bX_XXXX);
           assert (in[byte_count-1] != 1'bX);
 `endif
           r_out <= in[byte_count-1];

src/minipit.v

@@ -32,8 +32,8 @@ module minipit (
 
   always @(posedge clk) begin
     if (reset) begin
-      counter <= 10;  // TODO: don't auto-set a counter
-      current_count <= 0;
+      counter <= 16'd10;  // TODO: don't auto-set a counter
+      current_count <= 16'd0;
       r_counter_set <= 1;  // TODO: don't auto-enable a default counter
       divider_count <= 0;
       r_interrupting <= 0;
@@ -56,7 +56,7 @@ module minipit (
         current_count <= current_count;
       end
 
-      if (counter_set && (current_count == counter)) begin
+      if (counter_set && (current_count == (counter - 1))) begin
         // pull interrupt line high for one clock cycle
         r_interrupting <= 1;
         if (repeating) begin

src/project.v

@@ -37,9 +37,6 @@ module tt_um_jtag_example_stevej (
   assign uo_out[1] = interrupting;
   assign uo_out[0] = tdo;
 
-  wire reset;
-  assign reset = ~rst_n;
-
   jtag jtag0 (
       .tck(ui_in[0]),
       .tdi(ui_in[1]),

test/test.py

@@ -40,28 +40,28 @@ async def test_tms_five_high_for_reset(dut):
         await ClockCycles(dut.clk, 1)
         dut.ui_in.value = 0b0000_1000
         await ClockCycles(dut.clk, 1)
+        dut.ui_in.value = 0b0000_1001
+        await ClockCycles(dut.clk, 1)
+        dut.ui_in.value = 0b0000_1000
+        await ClockCycles(dut.clk, 1)
+
         assert dut.uo_out.value == 0x0
 
         # Drive TMS high then low for five cycles to put us into reset.
         dut._log.info("TMS high for five pulses to reset TAP controller")
         dut.ui_in.value = 0b0000_1111
         await ClockCycles(dut.clk, 1)
-        dut.ui_in.value = 0b0000_1110
-        await ClockCycles(dut.clk, 1)
 
-        dut.ui_in.value = 0b0000_1111
-        await ClockCycles(dut.clk, 1)
         dut.ui_in.value = 0b0000_1110
         await ClockCycles(dut.clk, 1)
-
         dut.ui_in.value = 0b0000_1111
         await ClockCycles(dut.clk, 1)
+
         dut.ui_in.value = 0b0000_1110
         await ClockCycles(dut.clk, 1)
-
         dut.ui_in.value = 0b0000_1111
         await ClockCycles(dut.clk, 1)
-        dut.ui_in.value = 0b0000_1110
+
         # At this point, the design is in reset but
         # the interrupt is also firing on all the other pins.
         assert dut.uo_out.value == 0xFE