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ARG VARIANT=ubuntu-22.04 | ||
FROM mcr.microsoft.com/vscode/devcontainers/base:${VARIANT} | ||
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ENV DEBIAN_FRONTEND=noninteractive | ||
ENV PDK_ROOT=~/ttsetup/pdk | ||
ENV PDK=sky130A | ||
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RUN apt update | ||
RUN apt install -y iverilog python3 python3-pip python3-venv python3-tk python-is-python3 libcairo2 verilator libpng-dev libqhull-dev | ||
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# Clone tt-support-tools | ||
RUN mkdir -p /ttsetup | ||
RUN git clone -b tt09 https://github.com/TinyTapeout/tt-support-tools /ttsetup/tt-support-tools | ||
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COPY test/requirements.txt /ttsetup/test_requirements.txt | ||
COPY .devcontainer/copy_tt_support_tools.sh /ttsetup | ||
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RUN pip3 install -r /ttsetup/test_requirements.txt -r /ttsetup/tt-support-tools/requirements.txt | ||
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# Install verible (for formatting) | ||
RUN umask 022 && \ | ||
curl -L https://github.com/chipsalliance/verible/releases/download/v0.0-3795-gf4d72375/verible-v0.0-3795-gf4d72375-linux-static-x86_64.tar.gz | \ | ||
tar zxf - -C /usr/local --strip-components=1 && \ | ||
chmod 755 /usr/local/bin | ||
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# Install openlane | ||
RUN pip3 install openlane==2.1.5 |
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#! /bin/sh | ||
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if [ ! -L tt ]; then | ||
cp -R /ttsetup/tt-support-tools tt | ||
cd tt && git pull && cd .. | ||
fi |
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// For format details, see https://aka.ms/devcontainer.json. For config options, see the README at: | ||
// https://github.com/microsoft/vscode-dev-containers/tree/v0.183.0/containers/ubuntu | ||
{ | ||
"name": "Tiny Tapeout Dev Container", | ||
"build": { | ||
"dockerfile": "Dockerfile", | ||
"context": ".." | ||
}, | ||
"runArgs": [ | ||
"--memory=10GB" | ||
], | ||
"customizations": { | ||
"vscode": { | ||
"settings": { | ||
"terminal.integrated.defaultProfile.linux": "bash" | ||
}, | ||
"extensions": ["mshr-h.veriloghdl", "surfer-project.surfer"] | ||
} | ||
}, | ||
"features": { | ||
"ghcr.io/devcontainers/features/docker-in-docker:2": { | ||
"moby": true, | ||
"azureDnsAutoDetection": true, | ||
"version": "latest", | ||
"dockerDashComposeVersion": "none" | ||
} | ||
}, | ||
"postStartCommand": "/ttsetup/copy_tt_support_tools.sh" | ||
} |
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name: docs | ||
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on: | ||
push: | ||
workflow_dispatch: | ||
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jobs: | ||
docs: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: Checkout repo | ||
uses: actions/checkout@v4 | ||
with: | ||
submodules: recursive | ||
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- name: Build docs | ||
uses: TinyTapeout/tt-gds-action/docs@tt09 |
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name: fpga | ||
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on: | ||
push: | ||
# Comment out (or remove) the following line to run the FPGA workflow on every push: | ||
branches: none | ||
workflow_dispatch: | ||
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jobs: | ||
fpga: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: checkout repo | ||
uses: actions/checkout@v4 | ||
with: | ||
submodules: recursive | ||
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- name: FPGA bitstream for TT ASIC Sim (ICE40UP5K) | ||
uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt09 |
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name: gds | ||
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on: | ||
push: | ||
workflow_dispatch: | ||
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jobs: | ||
gds: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: checkout repo | ||
uses: actions/checkout@v4 | ||
with: | ||
submodules: recursive | ||
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- name: Build GDS | ||
uses: TinyTapeout/tt-gds-action@tt09 | ||
with: | ||
flow: openlane2 | ||
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precheck: | ||
needs: gds | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: Run Tiny Tapeout Precheck | ||
uses: TinyTapeout/tt-gds-action/precheck@tt09 | ||
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gl_test: | ||
needs: gds | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: checkout repo | ||
uses: actions/checkout@v4 | ||
with: | ||
submodules: recursive | ||
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- name: GL test | ||
uses: TinyTapeout/tt-gds-action/gl_test@tt09 | ||
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viewer: | ||
needs: gds | ||
runs-on: ubuntu-latest | ||
permissions: | ||
pages: write # to deploy to Pages | ||
id-token: write # to verify the deployment originates from an appropriate source | ||
steps: | ||
- uses: TinyTapeout/tt-gds-action/viewer@tt09 |
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name: test | ||
on: [push, workflow_dispatch] | ||
jobs: | ||
test: | ||
runs-on: ubuntu-latest | ||
steps: | ||
- name: Checkout repo | ||
uses: actions/checkout@v4 | ||
with: | ||
submodules: recursive | ||
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- name: Install iverilog | ||
shell: bash | ||
run: sudo apt-get update && sudo apt-get install -y iverilog | ||
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# Set Python up and install cocotb | ||
- name: Setup python | ||
uses: actions/setup-python@v5 | ||
with: | ||
python-version: '3.11' | ||
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- name: Install Python packages | ||
shell: bash | ||
run: pip install -r test/requirements.txt | ||
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- name: Run tests | ||
run: | | ||
cd test | ||
make clean | ||
make | ||
# make will return success even if the test fails, so check for failure in the results.xml | ||
! grep failure results.xml | ||
- name: Test Summary | ||
uses: test-summary/[email protected] | ||
with: | ||
paths: "test/results.xml" | ||
if: always() | ||
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- name: upload vcd | ||
if: success() || failure() | ||
uses: actions/upload-artifact@v4 | ||
with: | ||
name: test-vcd | ||
path: | | ||
test/tb.vcd | ||
test/results.xml |
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.DS_Store | ||
.idea | ||
*.vcd | ||
runs | ||
tt_submission | ||
src/user_config.json | ||
src/config_merged.json | ||
test/sim_build | ||
test/__pycache__/ | ||
test/results.xml | ||
test/gate_level_netlist.v |
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{ | ||
"recommendations": [ | ||
"mshr-h.veriloghdl", | ||
"surfer-project.surfer" | ||
] | ||
} |
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{ | ||
"verilog.linting.linter": "verilator", | ||
"verilog.formatting.verilogHDL.formatter": "verible-verilog-format" | ||
} |
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