SystemVerilog and moving to logic #3
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| name: fpga | |
| on: | |
| push: | |
| # Comment out (or remove) the following line to run the FPGA workflow on every push: | |
| #branches: none | |
| workflow_dispatch: | |
| jobs: | |
| fpga: | |
| runs-on: ubuntu-24.04 | |
| steps: | |
| - name: checkout repo | |
| uses: actions/checkout@v4 | |
| with: | |
| submodules: recursive | |
| - name: FPGA bitstream for TT ASIC Sim (ICE40UP5K) | |
| uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt09 |