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SystemVerilog and moving to logic #59

SystemVerilog and moving to logic

SystemVerilog and moving to logic #59

Workflow file for this run

name: gds
on:
push:
workflow_dispatch:
jobs:
gds:
runs-on: ubuntu-24.04
steps:
- name: checkout repo
uses: actions/checkout@v4
with:
submodules: recursive
- name: Build GDS
uses: TinyTapeout/tt-gds-action@tt09
with:
flow: openlane2
precheck:
needs: gds
runs-on: ubuntu-latest
steps:
- name: Run Tiny Tapeout Precheck
uses: TinyTapeout/tt-gds-action/precheck@tt09
gl_test:
needs: gds
runs-on: ubuntu-24.04
steps:
- name: checkout repo
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install iverilog
shell: bash
run: |
sudo apt-get -qq remove iverilog
wget https://github.com/htfab/iverilog/releases/download/13.0-git-d8c3c51/iverilog_13.0-git-d8c3c51a-1_amd64.deb
sudo apt-get update -y
sudo apt-get install -y ./iverilog_13.0-git-d8c3c51a-1_amd64.deb
- name: GL test
uses: TinyTapeout/tt-gds-action/gl_test@tt09
viewer:
needs: gds
runs-on: ubuntu-latest
permissions:
pages: write # to deploy to Pages
id-token: write # to verify the deployment originates from an appropriate source
steps:
- uses: TinyTapeout/tt-gds-action/viewer@tt09