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stevej / tt09-jtag-example-v2-stevej Public

generated from TinyTapeout/tt09-verilog-template

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fpga

moving to always_ff #2

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moving to always_ff

moving to always_ff #2

Summary
Jobs
- fpga
Run details
- Usage
- Workflow file

Usage Workflow file

Annotations

1 error

FPGA bitstream for TT ASIC Sim (ICE40UP5K)

Process completed with exit code 1.

fpga

failed Nov 6, 2024 in 43s

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