adding back load-bearing empty module

stevej · Nov 2, 2023 · 42646ea · 42646ea
1 parent 2f21f20
commit 42646ea
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Showing 2 changed files with 10 additions and 1 deletion.
diff --git a/src/Makefile b/src/Makefile
@@ -9,7 +9,7 @@ TOPLEVEL_LANG ?= verilog
 ifneq ($(GATES),yes)
 
 # this is the only part you should need to modify:
-VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_minipit_stevej.v
+VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_minipit_stevej.v $(PWD)/minipit.v
 
 else
 

diff --git a/src/minipit.v b/src/minipit.v
@@ -0,0 +1,9 @@
+`default_nettype none
+`timescale 1ns/1ps
+
+
+module minipit();
+
+
+
+endmodule