Add Armv7M support for Cortex-M4 and Cortex-M7 #61
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regarding the pipeline models, I did some analysis on those already. |
* Introduces loop class for loops that restore the compare-to pointer using a vmov * Modifies mode of operation for loop extraction: The loop instructions need to appear in sequence
* Slight code modification to make loop parsable
Previously the selftest would determine which registers are supposed to contain addresses (and allocate memory accordingly) by going through all memory operations and assuming that address registers used in those are the inputs holding the addresses initially. This assumption does not hold as (1) addresses may be moved around (2) addresses may actually be a result of a previous computation. One example where this did not work was vmov rX, sY ldr tZ, [rX] here the selftest would assume that rX needs to be an address. However, sY is the register holding the address on entry of the code. This commit refines the code determining the address registers by recursively going through the DFG and determining the _input_ registers that affect values being used as addresses. Note that in the above examples rX would not be marked as an address, at it is not an input. Hopefully this approach is more robust.
This allows to access memory at negative offsets.
* Helps in case of ambigous loop types and makes the operation more predictable.
* Fix issue with wrong detection of FPR for storing end-pointer * Move to the end of loop classes (i.e., lowest priority) * Apply BranchLoop to ntt_dilithium example to get deprecate of boundary_reserved_regs
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Continuation of #55