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Tweak M7 uArch model: MAC issue slot constraint + MAC forwarding path #138

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3 changes: 3 additions & 0 deletions slothy/core/core.py
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,9 @@
class SlothyException(Exception):
"""Generic exception thrown by SLOTHY"""

class SlothySelfCheckException(SlothyException):
"""Exception thrown by SLOTHY during tht selfcheck """

class Result(LockAttributes):
"""The results of a one-shot SLOTHY optimization run"""

Expand Down
18 changes: 14 additions & 4 deletions slothy/targets/arm_v7m/cortex_m7.py
Original file line number Diff line number Diff line change
Expand Up @@ -56,11 +56,17 @@ def add_further_constraints(slothy):
add_st_hazard(slothy)

add_dsp_slot_constraint(slothy)
add_mac_slot_constraint(slothy)

def add_dsp_slot_constraint(slothy):
slothy.restrict_slots_for_instructions_by_class(
[pkhbt, pkhtb, pkhbt_shifted, ubfx_imm, uadd16, usub16, sadd16, ssub16], [0])

def add_mac_slot_constraint(slothy):
slothy.restrict_slots_for_instructions_by_class(
[mul, mul_short, smull, smlal, mla, mls, smulwb, smulwt, smultb, smultt,
smulbb, smlabt, smlabb, smlatt, smlad, smladx, smuad, smuadx, smmulr], [1])

# TODO: this seems incorrect
def add_slot_constraints(slothy):
slothy.restrict_slots_for_instructions_by_class(
Expand Down Expand Up @@ -285,12 +291,16 @@ def get_latency(src, out_idx, dst):
latency = lookup_multidict(default_latencies, src)

# Forwarding path to MAC instructions
if instclass_dst in [mla, mls, smlabb, smlabt, smlatt, smlatb] and src.args_out[0] == dst.args_in[2]:
if instclass_dst in [mla, mls, smlabb, smlabt, smlatt, smlatb] and dst.args_in[2] in (src.args_out + src.args_in_out):
latency = latency - 1

if instclass_dst in [smlal] and \
(src.args_out[0] == dst.args_in_out[0] or src.args_out[0] == dst.args_in_out[1]):
latency = latency - 1
if instclass_dst in [smlal]:
if len(src.args_out) > 1:
if (src.args_out[0] == dst.args_in_out[0] or src.args_out[0] == dst.args_in_out[1]):
latency = latency - 1
elif len(src.args_in_out) > 1:
if (src.args_in_out[0] == dst.args_in_out[0] or src.args_in_out[0] == dst.args_in_out[1]):
latency = latency - 1

# Multiply accumulate chain latency is 1
if instclass_src in [smlal] and instclass_dst in [smlal] and \
Expand Down
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