Add support for spilling to FPR in Armv7-M model

slothy/core/config.py

@@ -1004,6 +1004,22 @@ def allow_spills(self):
             be the case for symbolic input assembly."""
             return self._allow_spills
 
+        @property
+        def spill_type(self):
+            """The type of spills to generate
+
+            This is usually spilling to the stack, but other options may exist.
+            For example, on Armv7-M microcontrollers it can be useful to spill
+            from the GPR file to the FPR file.
+
+            The type of this configuration option is architecture dependent.
+            You should consult the `Spill` class in the target architecture
+            model to understand the options."""
+            if self._spill_type is None:
+                return {}
+            else:
+                return self._spill_type
+
         @property
         def minimize_spills(self):
             """Minimize number of stack spills
@@ -1062,6 +1078,7 @@ def __init__(self):
             self._allow_reordering = True
             self._allow_renaming = True
             self._allow_spills = False
+            self._spill_type = None
 
             self.lock()
 
@@ -1101,6 +1118,9 @@ def allow_renaming(self,val):
         @allow_spills.setter
         def allow_spills(self,val):
             self._allow_spills = val
+        @spill_type.setter
+        def spill_type(self,val):
+            self._spill_type = val
         @minimize_spills.setter
         def minimize_spills(self,val):
             self._minimize_spills = val

slothy/core/core.py

@@ -598,14 +598,16 @@ def _get_code(self, visualize_reordering):
         d = self.config.placeholder_char
 
         def gen_restore(reg, loc, vis):
-            yield SourceLine(self.config.arch.Stack.restore(reg, loc)).\
+            args = self.config.constraints.spill_type
+            yield SourceLine(self.config.arch.Spill.restore(reg, loc, **args)).\
                 set_length(self.fixlen).\
                 set_comment(vis).\
                 add_tag("is_restore", True).\
                 add_tag("reads", f"stack_{loc}")
 
         def gen_spill(reg, loc, vis):
-            yield SourceLine(self.config.arch.Stack.spill(reg, loc)).\
+            args = self.config.constraints.spill_type
+            yield SourceLine(self.config.arch.Spill.spill(reg, loc, **args)).\
                 set_length(self.fixlen).\
                 set_comment(vis).\
                 add_tag("is_spill", True).\

slothy/targets/aarch64/aarch64_neon.py

@@ -3117,13 +3117,10 @@ class cmge(ASimdCompare): # pylint: disable=missing-docstring,invalid-name
     inputs = ["Va", "Vb"]
     outputs = ["Vd"]
 
-
-class Stack:
+class Spill:
     def spill(reg, loc):
-        # TODO: Use store instruction
         return f"str {reg}, [sp, #STACK_LOC_{loc}]"
     def restore(reg, loc):
-        # TODO: Use load instruction
         return  f"ldr {reg}, [sp, #STACK_LOC_{loc}]"
 
 # In a pair of vins writing both 64-bit lanes of a vector, mark the