Matched lengths of EEM0[4..7], added note on schematics

sinara-hw · Jan 22, 2019 · a064cd1 · a064cd1
1 parent 9e5b8f4
commit a064cd1
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Showing 5 changed files with 3 additions and 3 deletions.
diff --git a/PCB/Mirny.PcbDoc b/PCB/Mirny.PcbDoc
diff --git a/PCB/Mirny.PrjPCB b/PCB/Mirny.PrjPCB
@@ -28,7 +28,7 @@ DItemRevisionGUID=
 ReportSuppressedErrorsInMessages=0
 FSMCodingStyle=eFMSDropDownList_OneProcess
 FSMEncodingStyle=eFMSDropDownList_OneHot
-OutputPath=Project Outputs for Mirny
+OutputPath=
 LogFolderPath=
 ManagedProjectGUID=
 IncludeDesignInRelease=0
@@ -205,7 +205,7 @@ ClassGenCCAutoRoomEnabled=1
 ClassGenNCAutoScope=None
 DItemRevisionGUID=
 GenerateClassCluster=0
-DocumentUniqueId=FVPGMBBD
+DocumentUniqueId=BKTWSJOM
 
 [ProjectVariant1]
 UniqueID=8A281219-7357-4AF0-900E-E72895C9A7C2
@@ -438,7 +438,7 @@ SCH_HasExpandLogicalToPhysicalSheets=-1
 SaveSettingsToOutJob=-1
 
 [Generic_EDE]
-OutputDir=Project Outputs for Mirny
+OutputDir=
 
 [OutputGroup1]
 Name=Netlist Outputs

diff --git a/PCB/Mirny.schdoc b/PCB/Mirny.schdoc
diff --git a/PCB/Supply_VCO.SchDoc b/PCB/Supply_VCO.SchDoc
diff --git a/PCB/VCO_OUT_channel.SchDoc b/PCB/VCO_OUT_channel.SchDoc