Merge remote-tracking branch 'origin/signal_name_style_rule_regex' in…

…to my_master
sconwayaus · Jul 23, 2024 · 8a0e50f · 8a0e50f
2 parents 8727f04 + fd79fa1
commit 8a0e50f
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Showing 2 changed files with 23 additions and 34 deletions.
diff --git a/verilog/analysis/checkers/signal_name_style_rule.cc b/verilog/analysis/checkers/signal_name_style_rule.cc
@@ -48,17 +48,11 @@ using verible::LintViolation;
 using verible::SyntaxTreeContext;
 using verible::matcher::Matcher;
 
-#define STYLE_DEFAULT_REGEX "[a-z_0-9]+"
-static std::string style_default_regex = STYLE_DEFAULT_REGEX;
+static constexpr absl::string_view style_default_regex = "[a-z_0-9]+";
 
-SignalNameStyleRule::SignalNameStyleRule() {
-  style_regex_ =
-      std::make_unique<re2::RE2>(style_default_regex, re2::RE2::Quiet);
-
-  kMessage =
-      absl::StrCat("Signal name does not match the naming convention ",
-                   "defined by regex pattern: ", style_regex_->pattern());
-}
+SignalNameStyleRule::SignalNameStyleRule()
+    : style_regex_(
+          std::make_unique<re2::RE2>(style_default_regex, re2::RE2::Quiet)) {}
 
 const LintRuleDescriptor &SignalNameStyleRule::GetDescriptor() {
   static const LintRuleDescriptor d{
@@ -67,17 +61,11 @@ const LintRuleDescriptor &SignalNameStyleRule::GetDescriptor() {
       .desc =
           "Checks that signal names conform to a naming convention defined by "
           "a RE2 regular expression. Signals are defined as \"a net, variable, "
-          "or port within a SystemVerilog design\".\n"
-          "Example common regex patterns:\n"
-          "  lower_snake_case: \"[a-z_0-9]+\"\n"
-          "  UPPER_SNAKE_CASE: \"[A-Z_0-9]+\"\n"
-          "  Title_Snake_Case: \"[A-Z]+[a-z0-9]*(_[A-Z0-9]+[a-z0-9]*)*\"\n"
-          "  Sentence_snake_case: \"([A-Z0-9]+[a-z0-9]*_?)([a-z0-9]*_*)*\"\n"
-          "  camelCase: \"([a-z0-9]+[A-Z0-9]*)+\"\n"
-          "  PascalCaseRegexPattern: \"([A-Z0-9]+[a-z0-9]*)+\"\n"
-          "RE2 regular expression syntax documentation can be found at "
-          "https://github.com/google/re2/wiki/syntax\n",
-      .param = {{"style_regex", STYLE_DEFAULT_REGEX,
+          "or port within a SystemVerilog design\". The default regex pattern "
+          "expects \"lower_snake_case\". Refer to "
+          "https://github.com/chipsalliance/verible/tree/master/verilog/tools/"
+          "lint#readme for more detail on verible regex patterns.",
+      .param = {{"style_regex", std::string(style_default_regex),
                  "A regex used to check signal names style."}},
   };
   return d;
@@ -98,30 +86,37 @@ static const Matcher &DataMatcher() {
   return matcher;
 }
 
+std::string SignalNameStyleRule::CreateViolationMessage() {
+  return absl::StrCat("Signal name does not match the naming convention ",
+                      "defined by regex pattern: ", style_regex_->pattern());
+}
+
 void SignalNameStyleRule::HandleSymbol(const verible::Symbol &symbol,
                                        const SyntaxTreeContext &context) {
   verible::matcher::BoundSymbolManager manager;
   if (PortMatcher().Matches(symbol, &manager)) {
     const auto *identifier_leaf = GetIdentifierFromPortDeclaration(symbol);
     const auto name = ABSL_DIE_IF_NULL(identifier_leaf)->get().text();
     if (!RE2::FullMatch(name, *style_regex_)) {
-      violations_.insert(
-          LintViolation(identifier_leaf->get(), kMessage, context));
+      violations_.insert(LintViolation(identifier_leaf->get(),
+                                       CreateViolationMessage(), context));
     }
   } else if (NetMatcher().Matches(symbol, &manager)) {
     const auto identifier_leaves = GetIdentifiersFromNetDeclaration(symbol);
     for (const auto *leaf : identifier_leaves) {
       const auto name = leaf->text();
       if (!RE2::FullMatch(name, *style_regex_)) {
-        violations_.insert(LintViolation(*leaf, kMessage, context));
+        violations_.insert(
+            LintViolation(*leaf, CreateViolationMessage(), context));
       }
     }
   } else if (DataMatcher().Matches(symbol, &manager)) {
     const auto identifier_leaves = GetIdentifiersFromDataDeclaration(symbol);
     for (const auto *leaf : identifier_leaves) {
       const auto name = leaf->text();
       if (!RE2::FullMatch(name, *style_regex_)) {
-        violations_.insert(LintViolation(*leaf, kMessage, context));
+        violations_.insert(
+            LintViolation(*leaf, CreateViolationMessage(), context));
       }
     }
   }
@@ -131,13 +126,7 @@ absl::Status SignalNameStyleRule::Configure(absl::string_view configuration) {
   using verible::config::SetRegex;
   absl::Status s = verible::ParseNameValues(
       configuration, {{"style_regex", SetRegex(&style_regex_)}});
-  if (!s.ok()) return s;
-
-  kMessage =
-      absl::StrCat("Signal name does not match the naming convention ",
-                   "defined by regex pattern: ", style_regex_->pattern());
-
-  return absl::OkStatus();
+  return s;
 }
 
 LintRuleStatus SignalNameStyleRule::Report() const {

diff --git a/verilog/analysis/checkers/signal_name_style_rule.h b/verilog/analysis/checkers/signal_name_style_rule.h
@@ -43,6 +43,8 @@ class SignalNameStyleRule : public verible::SyntaxTreeLintRule {
 
   static const LintRuleDescriptor &GetDescriptor();
 
+  std::string CreateViolationMessage();
+
   void HandleSymbol(const verible::Symbol &symbol,
                     const verible::SyntaxTreeContext &context) final;
 
@@ -55,8 +57,6 @@ class SignalNameStyleRule : public verible::SyntaxTreeLintRule {
 
   // A regex to check the style against
   std::unique_ptr<re2::RE2> style_regex_;
-
-  std::string kMessage;
 };
 
 }  // namespace analysis