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[prefetcher] Fix issue causing a race condition between cache access … #220

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[prefetcher] Fix issue causing a race condition between cache access … #220

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11 changes: 7 additions & 4 deletions src/prefetcher.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ uint64_t StreamPrefetcher::access(MemReq& req) {
profAccesses.inc();

uint64_t reqCycle = req.cycle;
uint64_t respCycle = parent->access(req);
uint64_t respCycle = reqCycle;

Address pageAddr = req.lineAddr >> 6;
uint32_t pos = req.lineAddr & (64-1);
Expand Down Expand Up @@ -139,7 +139,7 @@ uint64_t StreamPrefetcher::access(MemReq& req) {
if (prefetchPos < 64 && !e.valid[prefetchPos]) {
MESIState state = I;
MemReq pfReq = {req.lineAddr + prefetchPos - pos, GETS, req.childId, &state, reqCycle, req.childLock, state, req.srcId, MemReq::PREFETCH};
uint64_t pfRespCycle = parent->access(pfReq); // FIXME, might segfault
uint64_t pfRespCycle = parent->access(pfReq);
e.valid[prefetchPos] = true;
e.times[prefetchPos].fill(reqCycle, pfRespCycle);
profPrefetches.inc();
Expand Down Expand Up @@ -179,12 +179,15 @@ uint64_t StreamPrefetcher::access(MemReq& req) {
}

req.childId = origChildId;

// Demand access must be executed _after_ any prefetch accesses to avoid a race
// condition that could invalidate the demand request before returning.
respCycle = MAX(respCycle, parent->access(req));

return respCycle;
}

// nop for now; do we need to invalidate our own state?
uint64_t StreamPrefetcher::invalidate(const InvReq& req) {
return child->invalidate(req);
}