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const-qualify relevant methods in Coherence Controls and MemObject #120

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2 changes: 1 addition & 1 deletion src/cache.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@
Cache::Cache(uint32_t _numLines, CC* _cc, CacheArray* _array, ReplPolicy* _rp, uint32_t _accLat, uint32_t _invLat, const g_string& _name)
: cc(_cc), array(_array), rp(_rp), numLines(_numLines), accLat(_accLat), invLat(_invLat), name(_name) {}

const char* Cache::getName() {
const char* Cache::getName() const {
return name.c_str();
}

Expand Down
2 changes: 1 addition & 1 deletion src/cache.h
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ class Cache : public BaseCache {
public:
Cache(uint32_t _numLines, CC* _cc, CacheArray* _array, ReplPolicy* _rp, uint32_t _accLat, uint32_t _invLat, const g_string& _name);

const char* getName();
const char* getName() const;
void setParents(uint32_t _childId, const g_vector<MemObject*>& parents, Network* network);
void setChildren(const g_vector<BaseCache*>& children, Network* network);
void initStats(AggregateStat* parentStat);
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2 changes: 1 addition & 1 deletion src/coherence_ctrls.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@
* should probably have a class that deals with this with a real hash function
* (TODO)
*/
uint32_t MESIBottomCC::getParentId(Address lineAddr) {
uint32_t MESIBottomCC::getParentId(Address lineAddr) const {
//Hash things a bit
uint32_t res = 0;
uint64_t tmp = lineAddr;
Expand Down
22 changes: 11 additions & 11 deletions src/coherence_ctrls.h
Original file line number Diff line number Diff line change
Expand Up @@ -57,8 +57,8 @@ class CC : public GlobAlloc {
virtual uint64_t processInv(const InvReq& req, int32_t lineId, uint64_t startCycle) = 0;

//Repl policy interface
virtual uint32_t numSharers(uint32_t lineId) = 0;
virtual bool isValid(uint32_t lineId) = 0;
virtual uint32_t numSharers(uint32_t lineId) const = 0;
virtual bool isValid(uint32_t lineId) const = 0;
};


Expand Down Expand Up @@ -163,14 +163,14 @@ class MESIBottomCC : public GlobAlloc {
}

/* Replacement policy query interface */
inline bool isValid(uint32_t lineId) {
inline bool isValid(uint32_t lineId) const {
return array[lineId] != I;
}

//Could extend with isExclusive, isDirty, etc, but not needed for now.

private:
uint32_t getParentId(Address lineAddr);
uint32_t getParentId(Address lineAddr) const;
};


Expand All @@ -188,11 +188,11 @@ class MESITopCC : public GlobAlloc {
sharers.reset();
}

bool isEmpty() {
bool isEmpty() const {
return numSharers == 0;
}

bool isExclusive() {
bool isExclusive() const {
return (numSharers == 1) && (exclusive);
}
};
Expand Down Expand Up @@ -236,7 +236,7 @@ class MESITopCC : public GlobAlloc {
}

/* Replacement policy query interface */
inline uint32_t numSharers(uint32_t lineId) {
inline uint32_t numSharers(uint32_t lineId) const {
return array[lineId].numSharers;
}

Expand Down Expand Up @@ -403,8 +403,8 @@ class MESICC : public CC {
}

//Repl policy interface
uint32_t numSharers(uint32_t lineId) {return tcc->numSharers(lineId);}
bool isValid(uint32_t lineId) {return bcc->isValid(lineId);}
uint32_t numSharers(uint32_t lineId) const {return tcc->numSharers(lineId);}
bool isValid(uint32_t lineId) const {return bcc->isValid(lineId);}
};

// Terminal CC, i.e., without children --- accepts GETS/X, but not PUTS/X
Expand Down Expand Up @@ -491,8 +491,8 @@ class MESITerminalCC : public CC {
}

//Repl policy interface
uint32_t numSharers(uint32_t lineId) {return 0;} //no sharers
bool isValid(uint32_t lineId) {return bcc->isValid(lineId);}
uint32_t numSharers(uint32_t lineId) const {return 0;} //no sharers
bool isValid(uint32_t lineId) const {return bcc->isValid(lineId);}
};

#endif // COHERENCE_CTRLS_H_
2 changes: 1 addition & 1 deletion src/ddr_mem.h
Original file line number Diff line number Diff line change
Expand Up @@ -264,7 +264,7 @@ class DDRMemory : public MemObject {
uint32_t _domain, g_string& _name);

void initStats(AggregateStat* parentStat);
const char* getName() {return name.c_str();}
const char* getName() const {return name.c_str();}

// Bound phase interface
uint64_t access(MemReq& req);
Expand Down
2 changes: 1 addition & 1 deletion src/detailed_mem.h
Original file line number Diff line number Diff line change
Expand Up @@ -320,7 +320,7 @@ class MemControllerBase : public MemObject {
MemControllerBase(g_string _memCfg, uint32_t _cacheLineSize, uint32_t _sysFreqMHz, uint32_t _domain, g_string& _name);
virtual ~MemControllerBase();

const char* getName() { return name.c_str(); }
const char* getName() const { return name.c_str(); }
void enqueue(MemAccessEventBase* ev, uint64_t cycle);
uint64_t access(MemReq& req);
uint32_t tick(uint64_t sysCycle);
Expand Down
4 changes: 2 additions & 2 deletions src/dramsim_mem_ctrl.h
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ class DRAMSimMemory : public MemObject { //one DRAMSim controller
DRAMSimMemory(std::string& dramTechIni, std::string& dramSystemIni, std::string& outputDir, std::string& traceName, uint32_t capacityMB,
uint64_t cpuFreqHz, uint32_t _minLatency, uint32_t _domain, const g_string& _name);

const char* getName() {return name.c_str();}
const char* getName() const {return name.c_str();}

void initStats(AggregateStat* parentStat);

Expand Down Expand Up @@ -99,7 +99,7 @@ class SplitAddrMemory : public MemObject {
return respCycle;
}

const char* getName() {
const char* getName() const {
return name.c_str();
}

Expand Down
4 changes: 2 additions & 2 deletions src/mem_ctrls.h
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ class SimpleMemory : public MemObject {
public:
uint64_t access(MemReq& req);

const char* getName() {return name.c_str();}
const char* getName() const {return name.c_str();}

SimpleMemory(uint32_t _latency, g_string& _name) : name(_name), latency(_latency) {}
};
Expand Down Expand Up @@ -91,7 +91,7 @@ class MD1Memory : public MemObject {
//uint32_t access(Address lineAddr, AccessType type, uint32_t childId, MESIState* state /*both input and output*/, MESIState initialState, lock_t* childLock);
uint64_t access(MemReq& req);

const char* getName() {return name.c_str();}
const char* getName() const {return name.c_str();}

private:
void updateLatency();
Expand Down
2 changes: 1 addition & 1 deletion src/memory_hierarchy.h
Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ class MemObject : public GlobAlloc {
//Returns response cycle
virtual uint64_t access(MemReq& req) = 0;
virtual void initStats(AggregateStat* parentStat) {}
virtual const char* getName() = 0;
virtual const char* getName() const = 0;
};

/* Base class for all cache objects */
Expand Down
2 changes: 1 addition & 1 deletion src/prefetcher.h
Original file line number Diff line number Diff line change
Expand Up @@ -105,7 +105,7 @@ class StreamPrefetcher : public BaseCache {
public:
explicit StreamPrefetcher(const g_string& _name) : timestamp(0), name(_name) {}
void initStats(AggregateStat* parentStat);
const char* getName() { return name.c_str();}
const char* getName() const { return name.c_str();}
void setParents(uint32_t _childId, const g_vector<MemObject*>& parents, Network* network);
void setChildren(const g_vector<BaseCache*>& children, Network* network);

Expand Down
2 changes: 1 addition & 1 deletion src/trace_driver.h
Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,7 @@ class TraceDriverProxyCache : public BaseCache {
MemObject* parent;
public:
TraceDriverProxyCache(g_string& _name) : drv(nullptr), id(-1), name(_name) {}
const char* getName() {return name.c_str();}
const char* getName() const {return name.c_str();}

void setParents(uint32_t _childId, const g_vector<MemObject*>& parents, Network* network) {id = _childId; assert(parents.size() == 1); parent = parents[0];}; //FIXME: Support multi-banked caches...
void setChildren(const g_vector<BaseCache*>& children, Network* network) {panic("Should not be called, this must be terminal");};
Expand Down