Add changes requested by Ved during signoff

The following changes are applied:
- remove the 'Comments from PR' from the final document preparation
  (but retaining in the repository, so we can point to it)
- dropped the 'justification for fast-track'

header.adoc

@@ -60,7 +60,7 @@ Copyright 2022-2023 by RISC-V International.
 [preface]
 include::contributors.adoc[]
 
-include::comments-from-public-review.adoc[]
+// include::comments-from-public-review.adoc[]
 
 include::intro.adoc[]
 include::zicondops.adoc[]

intro.adoc

@@ -4,8 +4,8 @@ The Zicond extension defines a simple solution that provides most of the benefit
 The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand).
 Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other microarchitectural provisions.
 
-=== Suitability for Fast Track Extension Process
-This proposed extension meets the Fast Track criteria: it consists of two, simple R-form instructions, it addresses a wide range of use-cases for branchless sequences, it composes with the existing RISC-V instruction set, and is not expected to be contentious.
+// === Suitability for Fast Track Extension Process
+// This proposed extension meets the Fast Track criteria: it consists of two, simple R-form instructions, it addresses a wide range of use-cases f// or branchless sequences, it composes with the existing RISC-V instruction set, and is not expected to be contentious.
 
 === Motivation and use cases
 One of the shortcomings of RISC-V, compared to competing instruction set architectures, is the absence of conditional operations to support branchless code-generation: this includes conditional arithmetic, conditional select and conditional move operations.