[RVP] Add missing intrinsics

1. add missing intrinsics 2. fix wrong subext for several instructions 3. fix testsuit errors
riscvarchive · Apr 25, 2021 · 2bc5611 · 2bc5611
1 parent 06c8e46
commit 2bc5611
Show file tree

Hide file tree

Showing 11 changed files with 1,385 additions and 1,011 deletions.
diff --git a/gcc/config/riscv/riscv-builtins-rvp.def b/gcc/config/riscv/riscv-builtins-rvp.def
diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
@@ -101,10 +101,11 @@ struct riscv_builtin_description {
 AVAIL (hard_float, TARGET_HARD_FLOAT)
 AVAIL (zprv, TARGET_ZPRV)
 AVAIL (zpsf, TARGET_ZPSF)
+AVAIL (zpsf32, TARGET_ZPSF && !TARGET_64BIT)
+AVAIL (zpsf64, TARGET_ZPSF && TARGET_64BIT)
 AVAIL (zpn, TARGET_ZPN)
 AVAIL (zpn64, TARGET_ZPN && TARGET_64BIT)
 AVAIL (zpn32, TARGET_ZPN && !TARGET_64BIT)
-AVAIL (rvp, TARGET_ZPSF || TARGET_ZPN || TARGET_ZPRV)
 
 AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
 AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
@@ -411,7 +412,7 @@ riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
   gcc_assert (opno + call_expr_nargs (exp)
 	      == insn_data[icode].n_generator_args);
   for (int argno = 0; argno < call_expr_nargs (exp); argno++){
-    if (TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN)
+    if (TARGET_ZPN)
       riscv_rvp_prepare_builtin_arg (&ops[opno++], exp, argno, icode, has_target_p);
     else
       riscv_prepare_builtin_arg (&ops[opno++], exp, argno);

diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
@@ -44,8 +44,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 
   if (TARGET_ZPN)
     builtin_define ("__riscv_zpn");
+
   if (TARGET_ZPRV)
     builtin_define ("__riscv_zprv");
+
   if (TARGET_ZPSF)
     builtin_define ("__riscv_zpsf");
 

diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
@@ -35,6 +35,9 @@ DEF_RISCV_FTYPE (1, (DI, DI))
 DEF_RISCV_FTYPE (2, (SI, SI, SI))
 DEF_RISCV_FTYPE (2, (DI, DI, DI))
 DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, USI, USI))
+DEF_RISCV_FTYPE (2, (UDI, USI, USI))
 
 /* p extension function types */
 DEF_RISCV_FTYPE (1, (UIXLEN, USI))

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
@@ -5273,20 +5273,20 @@ riscv_vector_mode_supported_p (enum machine_mode mode)
 {
   if (mode == V4QImode
       || mode == V2HImode)
-    return (TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN) && !TARGET_64BIT;
+    return TARGET_ZPN && !TARGET_64BIT;
 
   if (mode == V8QImode
       || mode == V4HImode
       || mode == V2SImode)
-    return (TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN) && TARGET_64BIT;
+    return TARGET_ZPN && TARGET_64BIT;
 
   return false;
 }
 
 static enum machine_mode
 riscv_vectorize_preferred_simd_mode (scalar_mode mode)
 {
-  if (!(TARGET_ZPRV || TARGET_ZPSF || TARGET_ZPN))
+  if (!TARGET_ZPN)
    return word_mode;
 
   switch (mode)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
@@ -166,8 +166,7 @@
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,
-   dalu,dalu64,daluround,dcmp,dclip,dmul,dmac,dinsb,dpack,dbpick,dwext,
-   simd"
+   dalu,dalu64,daluround,dcmp,dclip,dmul,dmac,dinsb,dpack,dbpick,dwext"
   (cond [(eq_attr "got" "load") (const_string "load")
 
 	 ;; If a doubleword move uses these expensive instructions,