disassemble rs3 argument ('r' modifiler)

riscvarchive · Nov 9, 2021 · e78ce2b · e78ce2b
1 parent 1b71bd8
commit e78ce2b
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
@@ -311,6 +311,11 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 		 riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
 	  break;
 
+	case 'r':
+	  print (info->stream, "%s",
+		 riscv_gpr_names[EXTRACT_OPERAND (RS3, l)]);
+	  break;
+
 	case 'u':
 	  print (info->stream, "0x%x",
 		 (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);