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Added rm field in assembly for fcvt instructions and fixed default to…
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… dyn.
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pawks committed Jun 17, 2022
1 parent 20756b0 commit 7f29f2e
Showing 1 changed file with 14 additions and 7 deletions.
21 changes: 14 additions & 7 deletions opcodes/riscv-opc.c
Original file line number Diff line number Diff line change
Expand Up @@ -686,9 +686,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.w.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
{"fcvt.wu.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_W|MASK_RM, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
{"fcvt.d.w", 0, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_W, MASK_FCVT_D_W, match_opcode, 0 },
{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_WU|MASK_RM, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
{"fcvt.d.wu", 0, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_WU, MASK_FCVT_D_WU, match_opcode, 0 },
{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_D_S|MASK_RM, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
{"fcvt.d.s", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_D_S, MASK_FCVT_D_S, match_opcode, 0 },
{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
{"fcvt.s.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
{"fclass.d", 0, INSN_CLASS_D_OR_ZDINX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
Expand Down Expand Up @@ -743,10 +746,14 @@ const struct riscv_opcode riscv_opcodes[] =
{"fcvt.w.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
{"fcvt.wu.q", 0, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_W|MASK_RM, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
{"fcvt.q.w", 0, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_W, MASK_FCVT_Q_W, match_opcode, 0 },
{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_WU|MASK_RM, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
{"fcvt.q.wu", 0, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU, match_opcode, 0 },
{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_S|MASK_RM, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
{"fcvt.q.s", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_Q_S, MASK_FCVT_Q_S, match_opcode, 0 },
{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_Q_D|MASK_RM, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
{"fcvt.q.d", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_Q_D, MASK_FCVT_Q_D, match_opcode, 0 },
{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
{"fcvt.s.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
{"fcvt.d.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
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