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Make mstatus[VS] dirty when write to vstart #623

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merged 6 commits into from
Nov 29, 2024
Merged

Make mstatus[VS] dirty when write to vstart #623

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d294f61
Add vext runtime support
Yui5427 Nov 26, 2024
b2f49bf
Remove sys_enable_vext in dirty_v_context_if_present
Yui5427 Nov 26, 2024
79e6078
Make mstatus[VS] dirty when write to vstart
Yui5427 Nov 26, 2024
3cb64da
Make mstatus[FS] dirty when write to fp csrs
Yui5427 Nov 26, 2024
e6a8923
Drop dirty_fd_context
Yui5427 Nov 27, 2024
3c263fe
Drop changes of is_CSR_defined in vext
Yui5427 Nov 29, 2024
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3 changes: 0 additions & 3 deletions model/riscv_insts_vext_vset.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,6 @@
/* Chapter 6: Configuration-Setting Instructions */
/* ******************************************************************************* */

enum clause extension = Ext_V
function clause extensionEnabled(Ext_V) = (misa[V] == 0b1) & (mstatus[VS] != 0b00)

mapping sew_flag : string <-> bits(3) = {
"e8" <-> 0b000,
"e16" <-> 0b001,
Expand Down
19 changes: 11 additions & 8 deletions model/riscv_vext_control.sail
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Expand Up @@ -6,6 +6,9 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_V
function clause extensionEnabled(Ext_V) = (misa[V] == 0b1) & (mstatus[VS] != 0b00)

mapping clause csr_name_map = 0x008 <-> "vstart"
mapping clause csr_name_map = 0x009 <-> "vxsat"
mapping clause csr_name_map = 0x00A <-> "vxrm"
Expand All @@ -14,13 +17,13 @@ mapping clause csr_name_map = 0xC20 <-> "vl"
mapping clause csr_name_map = 0xC21 <-> "vtype"
mapping clause csr_name_map = 0xC22 <-> "vlenb"

function clause is_CSR_defined (0x008) = true
function clause is_CSR_defined (0x009) = true
function clause is_CSR_defined (0x00A) = true
function clause is_CSR_defined (0x00F) = true
function clause is_CSR_defined (0xC20) = true
function clause is_CSR_defined (0xC21) = true
function clause is_CSR_defined (0xC22) = true
function clause is_CSR_defined (0x008) = extensionEnabled(Ext_V)
function clause is_CSR_defined (0x009) = extensionEnabled(Ext_V)
function clause is_CSR_defined (0x00A) = extensionEnabled(Ext_V)
function clause is_CSR_defined (0x00F) = extensionEnabled(Ext_V)
function clause is_CSR_defined (0xC20) = extensionEnabled(Ext_V)
function clause is_CSR_defined (0xC21) = extensionEnabled(Ext_V)
function clause is_CSR_defined (0xC22) = extensionEnabled(Ext_V)

function clause read_CSR(0x008) = zero_extend(vstart)
function clause read_CSR(0x009) = zero_extend(vcsr[vxsat])
Expand All @@ -30,7 +33,7 @@ function clause read_CSR(0xC20) = vl
function clause read_CSR(0xC21) = vtype.bits
function clause read_CSR(0xC22) = get_vlenb()

function clause write_CSR(0x008, value) = { let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
function clause write_CSR(0x008, value) = { dirty_v_context(); let vstart_length = get_vlen_pow(); vstart = zero_extend(16, value[(vstart_length - 1) .. 0]); zero_extend(vstart) }
function clause write_CSR(0x009, value) = { ext_write_vcsr (vcsr[vxrm], value[0 .. 0]); zero_extend(vcsr[vxsat]) }
function clause write_CSR(0x00A, value) = { ext_write_vcsr (value[1 .. 0], vcsr[vxsat]); zero_extend(vcsr[vxrm]) }
function clause write_CSR(0x00F, value) = { ext_write_vcsr (value [2 .. 1], value [0 .. 0]); zero_extend(vcsr.bits) }
6 changes: 1 addition & 5 deletions model/riscv_vext_regs.sail
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Expand Up @@ -82,10 +82,6 @@ function dirty_v_context() -> unit = {
mstatus[SD] = 0b1
}

function dirty_v_context_if_present() -> unit = {
if sys_enable_vext() then dirty_v_context()
}

function rV (r : regno) -> vregtype = {
match r {
0 => vr0,
Expand Down Expand Up @@ -222,7 +218,7 @@ val ext_write_vcsr : (bits(2), bits(1)) -> unit
function ext_write_vcsr (vxrm_val, vxsat_val) = {
vcsr[vxrm] = vxrm_val; /* Note: frm can be an illegal value, 101, 110, 111 */
vcsr[vxsat] = vxsat_val;
dirty_v_context_if_present()
dirty_v_context()
}

/* num_elem means max(VLMAX,VLEN/SEW)) according to Section 5.4 of RVV spec */
Expand Down
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