Merge pull request #49 from riscv/jhauser-2023-1.0

Update to ratified version 1.0
riscv · Jul 1, 2023 · f24dd48 · f24dd48
2 parents 0dce52d + 3756b91
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diff --git a/doc/src/AdvPLIC.tex b/doc/src/AdvPLIC.tex
@@ -4,12 +4,6 @@ \chapter{Advanced Platform-Level Interrupt Controller (APLIC)}
 \label{ch:AdvPLIC}
 \chaptermark{APLIC}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 In a {\RISCV} system, a Platform-Level Interrupt Controller (PLIC)
 handles external interrupts that are signaled through wires rather than
 by MSIs.

diff --git a/doc/src/CSRs.tex b/doc/src/CSRs.tex
@@ -4,12 +4,6 @@ \chapter{Control and Status Registers (CSRs) Added to Harts}
 \label{ch:CSRs}
 \chaptermark{CSRs Added to Harts}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 For each privilege level at which a {\RISCV} hart can take interrupt
 traps, the Advanced Interrupt Architecture adds CSRs for interrupt
 control and handling.

diff --git a/doc/src/IMSIC.tex b/doc/src/IMSIC.tex
@@ -4,12 +4,6 @@ \chapter{Incoming MSI Controller (IMSIC)}
 \label{ch:IMSIC}
 \chaptermark{IMSIC}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 An Incoming MSI Controller (IMSIC) is an optional {\RISCV} hardware
 component that is closely coupled with a hart, one IMSIC per hart.
 An IMSIC receives and records incoming message-signaled interrupts

diff --git a/doc/src/IOMMU.tex b/doc/src/IOMMU.tex
@@ -3,12 +3,6 @@
 \chapter{IOMMU Support for MSIs to Virtual Machines}
 \label{ch:IOMMU}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 The existence of an \mbox{IOMMU} in a system makes it possible for a guest
 operating system, running in a virtual machine, to be given direct
 control of an I/O device with only minimal hypervisor intervention.

diff --git a/doc/src/IPIs.tex b/doc/src/IPIs.tex
@@ -3,12 +3,6 @@
 \chapter{Interprocessor Interrupts (IPIs)}
 \label{ch:IPIs}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 By default, unless a platform has a different mechanism for
 interprocessor interrupts (IPIs), the {\RISCV} Privileged Architecture
 specifies that a machine with multiple harts must provide for each hart

diff --git a/doc/src/MSLevel.tex b/doc/src/MSLevel.tex
@@ -3,12 +3,6 @@
 \chapter{Interrupts for Machine and Supervisor Levels}
 \label{ch:MSLevel}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 The {\RISCV} Privileged Architecture defines several major identities
 in the range 0--15 for interrupts at a hart, including machine-level
 and supervisor-level external interrupts (numbers 11 and~9), machine-

diff --git a/doc/src/VSLevel.tex b/doc/src/VSLevel.tex
@@ -3,12 +3,6 @@
 \chapter{Interrupts for Virtual Machines (VS Level)}
 \label{ch:VSLevel}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 When the hypervisor extension is implemented, a hart's set of possible
 privilege modes includes the \emph{virtual supervisor} (VS) and
 \emph{virtual user} (VU) modes for hosting virtual harts.

diff --git a/doc/src/intro.tex b/doc/src/intro.tex
@@ -3,12 +3,6 @@
 \chapter{Introduction}
 \label{ch:intro}
 
-\textbf{%
-This chapter is \emph{frozen} and has already passed public review,
-making a functional change at this stage extremely unlikely.%
-}
-\bigskip
-
 This document specifies the Advanced Interrupt Architecture for
 {\RISCV}, consisting of:
 (a)~an extension to the standard Privileged Architecture for {\RISCV}
@@ -166,6 +160,8 @@ \section{Limits}
 specific organization, which we do not attempt to predict.
 \end{commentary}
 
+\FloatBarrier
+
 %-----------------------------------------------------------------------
 \section{Overview of main components}
 

diff --git a/doc/src/preface.tex b/doc/src/preface.tex
@@ -4,46 +4,41 @@ \chapter{Preface}
 
 This document describes an Advanced Interrupt Architecture
 for {\RISCV} systems.
+This specification was ratified by the
+{\RISCV} International Association in June of 2023.
 
-No part of this document has yet been ratified
-by the {\RISCV} International Association.
-The table below shows the current status of each chapter,
-and also indicates which chapters specify extensions to the
+The table below indicates which chapters
+of this document specify extensions to the
 {\RISCV} ISA (instruction set architecture) and which are non-ISA.
 
 {
 \begin{table}[hbt]
 \centering
-\begin{tabular}{|l|c|c|}
+\begin{tabular}{|l|c|}
 \hline
-Chapter                                                  & ISA? & Status \\
+Chapter                                                  & ISA? \\
 \hline
 \hline
-1.\ Introduction                                         & ---  & Frozen \\
-2.\ Control and Status Registers (CSRs) Added to Harts   & Yes  & Frozen \\
-3.\ Incoming MSI Controller (IMSIC)                      & Yes  & Frozen \\
-4.\ Advanced Platform-Level Interrupt Controller (APLIC) & No   & Frozen \\
-5.\ Interrupts for Machine and Supervisor Levels         & Yes  & Frozen \\
-6.\ Interrupts for Virtual Machines (VS Level)           & Yes  & Frozen \\
-7.\ Interprocessor Interrupts (IPIs)                     & No   & Frozen \\
-8.\ IOMMU Support for MSIs to Virtual Machines           & No   & Frozen \\
+1.\ Introduction                                         & ---  \\
+2.\ Control and Status Registers (CSRs) Added to Harts   & Yes  \\
+3.\ Incoming MSI Controller (IMSIC)                      & Yes  \\
+4.\ Advanced Platform-Level Interrupt Controller (APLIC) & No   \\
+5.\ Interrupts for Machine and Supervisor Levels         & Yes  \\
+6.\ Interrupts for Virtual Machines (VS Level)           & Yes  \\
+7.\ Interprocessor Interrupts (IPIs)                     & No   \\
+8.\ IOMMU Support for MSIs to Virtual Machines           & No   \\
 \hline
 \end{tabular}
 \end{table}
 }
 
-An implementation adhering to the current document might not conform
-to an eventual ratified Advanced Interrupt Architecture for {\RISCV}.
-However, all chapters are \emph{frozen}, meaning they are not expected
-to change significantly before being put up for ratification.
-
-\section*{Changes for RC6 (Ratification Candidate 6)}
+\section*{Changes for the ratified version 1.0}
 
 Resolved some inconsistencies in Chapter~\ref{ch:CSRs}
 about when to raise a virtual instruction exception
 versus an illegal instruction exception.
 
-\section*{Changes for RC5}
+\section*{Changes for RC5 (Ratification Candidate 5)}
 
 Better aligned the rules for indirectly accessed registers with the
 hypervisor extension and with forthcoming extension Smcsrind/Sscsrind.
@@ -90,8 +85,7 @@ \section*{Changes for RC3}
 
 \section*{Changes for RC2}
 
-The only normative changes to this document
-between versions RC1 and RC2 were to clarify that
+Clarified that
 field IID of CSR \z{hvictl} must support all
 unsigned integer values of the number of bits implemented
 for that field, and that writes to \z{hvictl}

diff --git a/doc/src/riscv-interrupts.tex b/doc/src/riscv-interrupts.tex
@@ -11,7 +11,7 @@
 
 \input{preamble}
 
-\newcommand{\AIARev}{1.0-RC6}
+\newcommand{\AIARev}{1.0}
 \newcommand{\AIAMonthYear}{Month YEAR}
 
 \setcounter{secnumdepth}{3}
@@ -35,7 +35,7 @@
 \title{%
   \vspace{-0.7in}%
   {\Large\bf The RISC-V Advanced Interrupt Architecture} \\
-  {\large Document Version \AIARev}
+  {\large Version \AIARev}
   \vspace{-0.1in}%
 }