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Fix https://github.com/riscv-non-isa/riscv-brs/issues/168 #171

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May 31, 2024
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Fix https://github.com/riscv-non-isa/riscv-brs/issues/168 #171

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2 changes: 1 addition & 1 deletion smbios.adoc
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Expand Up @@ -44,7 +44,7 @@ A processor is a grouping of harts in a physical package. In modern designs this
For RISC-V class CPUs, the `Processor ID` field contains two `DWORD`-formatted values describing
the overall physical processor package vendor and version. For some implementations
this may also be known as the SoC ID. The first `DWORD` (offsets 08h-0Bh) is the JEP-106 code for
the vendor. The second `DWORD` (offsets 0Ch-0Fh) reflects vendor-specific part versioning.
the vendor, where bits 6:0 is the ID without the parity and bits 31:7 represent the number of continuation codes. The second `DWORD` (offsets 0Ch-0Fh) reflects vendor-specific part versioning.

For hart-specific vendor and revision information, please see Type 44 Processor-Specific Data structures.

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