[DO NOT MERGE] mmc: host: bcm2835: Capture MMC errors #6475

The BCM2712 has a completely different HVS than the previous generations, so let's add a new compatible for it. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 has 3 different pixelvalves that are similar to the ones found in the previous generations but with slightly different capabilities. Express that using a new set of compatibles. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 has a MOP controller which is basically a new revision of the TXP. Express that by adding a new compatible for it. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 has a MOPLET controller which is basically a TXP without the transpose feature. Express that by adding a new compatible for it. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 SoC comes with a new variation of the videocore display pipeline. Let's create a new compatible for it. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 has an improved display pipeline, most notably with a different HVS and only HDMI and writeback outputs. Let's introduce it as a new VideoCore generation and compatible. Signed-off-by: Maxime Ripard <[email protected]>

The HVS found in the BCM2712, while having a similar role, is very different from the one found in the previous SoCs. Indeed, the register layout is fairly different, and the DLIST format is new as well. Let's introduce the needed functions to support the new HVS. Signed-off-by: Maxime Ripard <[email protected]> drm/vc4: Fix atomic_async_check to call the right mode_set function vc4_plane_atomic_async_check was always calling vc4_plane_mode_set to validate and generate the dlist for the check. If async_check decided it had to fall back to a sync commit, then this GEN4/5 dlist could get used on GEN6. Call either vc4_plane_mode_set or vc6_plane_mode_set as appropriate. Fixes: 1ab1fbb ("drm/vc4: hvs: Support BCM2712 HVS") Signed-off-by: Dave Stevenson <[email protected]> drm/vc4: Add 2712 support to vc4_plane_async_set_fb vc4_plane_async_set_fb directly overwrites the plane address in the dlist entry, but hadn't been updated for the GEN6 / 2712 dlist format, corrupting the address in the process. Add support for the 2712 dlist format to the function. Fixes: 1ab1fbb ("drm/vc4: hvs: Support BCM2712 HVS") Signed-off-by: Dave Stevenson <[email protected]>

The PixelValves found on the BCM2712 are similar to the ones found in the previous generation. Compared to BCM2711, the pixelvalves only drive one HDMI controller each and HDMI1 PixelValve has a FIFO long enough to support 4k at 60Hz. Signed-off-by: Maxime Ripard <[email protected]>

The HDMI controllers found in the BCM2712 are largely the ones found in the BCM2711 with a different PHY. There's some difference with how timings are split between registers, and HDMI1 is now able to run at 4k/60Hz. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 will have several TXP with small differences. Let's add a structure tied to the compatible to deal with those differences. Signed-off-by: Maxime Ripard <[email protected]>

The TXP data structure has a name too generic for the multiple variants we'll have to support. Let's rename it to mention the SoC it applies to. Signed-off-by: Maxime Ripard <[email protected]>

The MOPLET doesn't have the BYTE_ENABLE field to set, but the TXP and MOP do, so let's add a boolean to control whether or not we need to set it. Signed-off-by: Maxime Ripard <[email protected]>

The new writeback controllers that can be found on the BCM2712 require to have their horizontal and vertical size reduced by one. Let's tie that behaviour to the compatible so we can support both the new and old controllers. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 MOP and MOPLET can handle addresses larger than 32bits through an extra register. We can easily support it and make it conditional based on the compatible through a boolean in our variant structure. Signed-off-by: Maxime Ripard <[email protected]>

We'll have multiple TXP instances in the BCM2712, so we can't use a single encoder type anymore. Let's tie the encoder type to the compatible. Signed-off-by: Maxime Ripard <[email protected]>

Starting with BCM2712, we'll have a two TXP. Let's follow the HDMI example and add two encoder types for TXP: TXP0 and TXP1. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 has an evolution of what used to be called TXP in the earlier SoCs, but is now called MOP. There's a few differences still, so we can add a new compatible to deal with them easily. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 features a simpler TXP called MOPLET. Let's add support for it. Signed-off-by: Maxime Ripard <[email protected]>

Some code path in vc4 are conditional to a generation and cannot be executed on others. Let's put a WARN_ON if that ever happens. Signed-off-by: Maxime Ripard <[email protected]>

Testing whether the VideoCore generation we want to mock is vc5 or vc4 worked so far, but will be difficult to extend to support BCM2712 (VC6). Convert to a switch. Signed-off-by: Maxime Ripard <[email protected]>

The DRM device pointer and the DRM encoder pointer are redundant, since the latter is attached to the former and we can just follow the drm_encoder->dev pointer. Let's remove the drm_device pointer argument. Signed-off-by: Maxime Ripard <[email protected]>

Some tests will need to retrieve the output that was just allocated by vc4_mock_atomic_add_output(). Instead of making them look them up in the DRM device, we can simply make vc4_mock_atomic_add_output() return an error pointer that holds the allocated output instead of the error code. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 has a simpler pipeline that can only output to a writeback connector and two HDMI controllers. Let's allow our kunit tests to create a mock of that pipeline. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 has a simpler pipeline than the BCM2711, and thus the muxing requirements are different. Create some tests to make sure we get proper muxing decisions. Signed-off-by: Maxime Ripard <[email protected]>

The current mock planes were just using the regular drm_plane_state, while the driver expect struct vc4_plane_state that subclasses drm_plane_state. Hook the proper implementations of reset, duplicate_state, destroy and atomic_check to create vc4_plane_state. Signed-off-by: Maxime Ripard <[email protected]>

Some tests will need to find a plane to run a test on for a given CRTC. Let's create a small helper to do that. Signed-off-by: Maxime Ripard <[email protected]>

We'll start to add some tests for the plane state logic, so let's create a helper to add a plane to an existing atomic state. Signed-off-by: Maxime Ripard <[email protected]>

We'll start testing our planes code in situations where we will use more than XRGB8888, so let's add a few common pixel formats. Signed-off-by: Maxime Ripard <[email protected]>

The BCM2712 comes with a different LBM size computation than the previous generations, so let's add the few examples provided as kunit tests to make sure we always satisfy those requirements. Signed-off-by: Maxime Ripard <[email protected]>

On 2712, the firmware always runs these clock at a speed sufficient for dual 4kp60. The requests here prevent the gpu from going into its lowest voltage mode, so just skip the clock requests. With this applied the idle voltage on my pi 5 reduces from 0.7424V to 0.72V. Signed-off-by: Dom Cobley <[email protected]>

It was accidentally placed in the audio decoder section. Signed-off-by: Naushir Patuck <[email protected]>

Allow DT aliases of eg DSI2 to force make DRM allocate the display with the requested name. Signed-off-by: Dave Stevenson <[email protected]>

Since "drm/vc4: hvs: Support BCM2712 HVS" booting Pi4 with dual 4kp30 displays connected fails with: vc4-drm gpu: [drm] *ERROR* [CRTC:107:pixelvalve-4] flip_done timed out It has been tracked down to the referenced commit adding a path to clear the SCALER_DISPBKGND_FILL when not required. Dual 4kp30 works with a core clock of 297MHz when background fill is enabled, but requires a higher value with it disabled. 320MHz still fails, while 330MHz seems okay. Lets always enable background fill for Pi0-4. Fixes: e84da23 ("drm/vc4: hvs: Support BCM2712 HVS") Signed-off-by: Dom Cobley <[email protected]>

Vision Components have made an OV9281 module which blocks reading back the majority of registers to comply with NDAs, and in doing so doesn't allow auto-increment register reading as used when reading the chip ID. Use two reads and manually combine the results. Signed-off-by: Dave Stevenson <[email protected]>

11cf37e switched to using drm_fb_dma_get_gem_addr instead of drm_fb_dma_get_gem_obj and adding fb->offset[]. However the tiled formats need to compute the offset in a more involved manner than drm_fb_dma_get_gem_addr applies, and we were ending up with the offset for src_[xy] being applied twice. Switch back to using drm_fb_dma_get_gem_obj and fully computing the offsets ourselves. Fixes: 11cf37e ("drm/vc4: Move the buffer offset out of the vc4_plane_state") Signed-off-by: Dave Stevenson <[email protected]>

Add a flag custom_fb_num to denote that the client has requested a specific fbdev node number via node. Signed-off-by: Dave Stevenson <[email protected]>

For situations where there are multiple DRM cards in a system, add a query of DT for "drm_fb" designations for cards to set their preferred /dev/fbN designation. Signed-off-by: Dave Stevenson <[email protected]> drm/fb_helper: Change query for FB designation from drm_fb to drm-fb Fixes: 1216ea5 ("drm/fb-helper: Look up preferred fbdev node number from DT") Signed-off-by: Dave Stevenson <[email protected]>

Apparently aliases are only allowed lower case and hyphens, so swap the use of underscore to hyphen. Fixes: 3aa1f24 ("drm: Look for an alias for the displays to use as the DRM device name") Signed-off-by: Dave Stevenson <[email protected]>

This property can be used to delay deassertion of external fundamental reset, which may be useful for endpoints that require an extended time for internal setup to complete. Signed-off-by: Jonathan Bell <[email protected]>

When factoring out __vc4_hvs_stop_channel, the logic got inverted from if (condition) // stop channel to if (condition) goto out //stop channel out: and also changed the exact register writes used to stop the channel. Correct the logic so that the channel is actually stopped, and revert to the original register writes. Fixes: 6d01a10 ("drm/vc4: crtc: Move HVS init and close to a function") Signed-off-by: Dave Stevenson <[email protected]>

The reset condition for the EMPTY flag in DISPSTATx is 0, so seeing as we've just reset the pipeline there is no guarantee that the flag will denote empty if it hasn't been enabled. Drop the WARN. Signed-off-by: Dave Stevenson <[email protected]>

The code handling freeing stale dlists had 2 issues: - it disabled the interrupt as soon as the first EOF interrupt occurred, even if it didn't clear all stale allocations, thus leading to stale entries - It didn't free stale entries from disabled channels, so eg "kmstest -c 0" could leave a stale alloc on channel 1 floating around. Keep the interrupt enabled whilst there are any outstanding allocs, and discard those on disabled channels. This second channel does require us to call vc4_hvs_stop_channel from vc4_crtc_atomic_disable so that the channel actually gets stopped. Signed-off-by: Dave Stevenson <[email protected]>

Users are reporting running out of DLIST memory. Add a debugfs file to dump out all the allocations. Signed-off-by: Dave Stevenson <[email protected]>

Signed-off-by: Dave Stevenson <[email protected]>

BCM2711 runs pixelvalve at two pixels per clock cycle which results in an unfortunate limitation that odd horizontal timings are not possible. This is apparent on the standard DMT mode of 1366x768@60 which cannot be driven with correct timing. BCM2712 defaults to the same behaviour, but has a mode to support odd timings. While internally it still runs at two pixels per clock, setting the PV_VCONTROL_ODD_TIMING bit makes it appear externally to behave as it is one pixel per clock. Switching to this mode fixes 1366x768@60 mode, and other custom resultions with odd horizontal timings. Signed-off-by: Dom Cobley <[email protected]> drm/vc4: Disable the 2pixel/clock odd timings workaround for interlaced Whilst BCM2712 does fix using odd horizontal timings, it doesn't work with interlaced modes. Drop the workaround for interlaced modes and revert to the same behaviour as BCM2711. raspberrypi#6281 Signed-off-by: Dave Stevenson <[email protected]>

Certain controllers (dwc-mshc) generate timeout conditions separately to command-completion conditions, where the end result is interrupts are separated in time depending on the current SDCLK frequency. This causes spurious interrupts if SDCLK is slow compared to the CPU's ability to process and return from interrupt. This occurs during card probe with an empty slot where all commands that would generate a response time out. Add a quirk to squelch command response interrupts when a command timeout interrupt is received. Signed-off-by: Jonathan Bell <[email protected]>

The DWC MSHC controller on RP1 needs differentiating from the generic version. Signed-off-by: Jonathan Bell <[email protected]>

Signed-off-by: Nick Bulleid <[email protected]> Added export feature to gpio-poweroff documentation Signed-off-by: Nick Bulleid <[email protected]>

With the new support for a chain of sys_off handlers, gpio-poweroff does not disable a normal shutdown (though it does delay it). There is therefore no need for the noisy WARN from the kernel. Signed-off-by: Phil Elwell <[email protected]>

See: https://forums.raspberrypi.com/viewtopic.php?p=2159344 Signed-off-by: Phil Elwell <[email protected]>

Users have reported log spam created by "Event Ring Full" xHC event TRBs. These are caused by interrupt latency in conjunction with a very busy set of devices on the bus. The errors are benign, but throughput will suffer as the xHC will pause processing of transfers until the event ring is drained by the kernel. Expand the number of event TRB slots available by increasing the number of event ring segments in the ERST. Controllers have a hardware-defined limit as to the number of ERST entries they can process, so make the actual number in use min(ERST_MAX_SEGS, hw_max). Signed-off-by: Jonathan Bell <[email protected]>

Step wise governor increases the mitigation level when the temperature goes above a threshold and will decrease the mitigation when the temperature falls below the threshold. If it were a case, where the temperature hovers around a threshold, the mitigation will be applied and removed at every iteration. This reaction to the temperature is inefficient for performance. The use of hysteresis temperature could avoid this ping-pong of mitigation by relaxing the mitigation to happen only when the temperature goes below this lower hysteresis value. Signed-off-by: Ram Chandrasekar <[email protected]> Signed-off-by: Lina Iyer <[email protected]> drivers: thermal: step_wise: avoid throttling at hysteresis temperature after dropping below it Signed-off-by: Serge Schneider <[email protected]> Fix hysteresis support in gov_step_wise.c Directly get hyst value instead of going through an optional and, now, unimplemented function. Signed-off-by: Jürgen Kreileder <[email protected]>

The mainline driver has implemented analogue gain using the control V4L2_CID_GAIN instead of V4L2_CID_ANALOGUE_GAIN. libcamera requires V4L2_CID_ANALOGUE_GAIN, and therefore fails. Update the driver to use V4L2_CID_ANALOGUE_GAIN. Signed-off-by: Dave Stevenson <[email protected]>

It is permitted for a plane to be configured such that none of it is on-screen via either negative dest rectangle X,Y offset, or just an offset that is greater than the crtc dimensions. These planes were resized via drm_atomic_helper_check_plane_state such that the source rectangle had a zero width or height, but they still created a dlist entry even though they contributed no pixels. In the case of vc6_plane_mode_set, that it could result in negative values being written into registers, which caused incorrect behaviour. Drop planes that result in a source width or height of 0 pixels to avoid the incorrect rendering. Signed-off-by: Dave Stevenson <[email protected]>

Commit 7cd7065 ("drm/bridge: display-connector: implement bus fmts callbacks") added use of drm_atomic_helper_bridge_* functions, but didn't select the dependency of DRM_KMS_HELPER. If nothing else selected that dependency it resulted in a build failure. Select the missing dependency. Fixes: 7cd7065 ("drm/bridge: display-connector: implement bus fmts callbacks") Signed-off-by: Dave Stevenson <[email protected]>

atomic_check creates a state, and allocates the dlist memory for it such that atomic_flush can not fail. On destroy that dlist allocation was being put in the stale list, even though it had never been programmed into the hardware, therefore doing lots of atomic_checks could consume all the dlist memory and fail. If the dlist has never been programmed into the hardware, then free it immediately. Signed-off-by: Dave Stevenson <[email protected]>

The dmabuf import already checks that the backing buffer is contiguous and rejects it if it isn't. vc4 also requires that the buffer is in the bottom 1GB of RAM, and this is all correctly defined via dma-ranges. However the kernel silently uses swiotlb to bounce dma buffers around if they are in the wrong region. This relies on dma sync functions to be called in order to copy the data to/from the bounce buffer. DRM is based on all memory allocations being coherent with the GPU so that any updates to a framebuffer will be acted on without the need for any additional update. This is fairly fundamentally incompatible with needing to call dma_sync_ to handle the bounce buffer copies, and therefore we have to detect and reject mappings that use bounce buffers. Signed-off-by: Dave Stevenson <[email protected]>

The moplet registers as VC4_ENCODER_TYPE_TXP1 and can be fed from mux output 2 of HVS channel 1. Correct the option which checked for VC4_ENCODER_TYPE_TXP0 Signed-off-by: Dave Stevenson <[email protected]>

MOP uses register offset 0x24 for the high bits of the address, whilst Moplet uses 0x1c. Handle this difference between the block types. Signed-off-by: Dave Stevenson <[email protected]>

Add YAML device tree bindings for the ROHM BU64754 VCM Motor Driver for Camera Autofocus. Signed-off-by: Kieran Bingham <[email protected]> Signed-off-by: Jacopo Mondi <[email protected]>

Add support for the ROHM BU64754 Motor Driver for Camera Autofocus. A V4L2 Subdevice is registered and provides a single V4L2_CID_FOCUS_ABSOLUTE control. Signed-off-by: Kieran Bingham <[email protected]> Signed-off-by: Jacopo Mondi <[email protected]>

Pi 5 uses BL31 as its armstub file, so the reset goes via PSCI. Parse any "reboot" parameter as a partition number to reboot into. N.B. This code path is only used if reboot mode has been set to warm or soft. Signed-off-by: Phil Elwell <[email protected]>

The frame count values moved within registers DISPSTAT1 and DISPSTAT2 with GEN5, so update the accessor function to accommodate that. Fixes: b51cd7a ("drm/vc4: hvs: Fix frame count register readout") Signed-off-by: Dave Stevenson <[email protected]>

Fixes: d869ef6a96a3 ("drm/vc4: Add debugfs node that dumps the vc5 gamma PWL entries") Signed-off-by: Dave Stevenson <[email protected]>

CSI2 devices are meant to use the 1Xnn formats rather than 2Xnn such as MEDIA_BUS_FMT_UYVY8_2X8. For devices with ADV7180_FLAG_MIPI_CSI2 set, use MEDIA_BUS_FMT_UYVY8_1X16. Signed-off-by: Dave Stevenson <[email protected]>

For CSI2 receivers that need to know the link frequency, add it as a control to the driver. Interlaced modes are 216Mbp/s or 108MHz, whilst going through the I2P to deinterlace gives 432Mb/s or 216MHz. Signed-off-by: Dave Stevenson <[email protected]>

The forced conversion of native CS lines into software CS lines is done whether or not the controller has been given any CS lines to use. This breaks the use of the spi0-0cs overlay to prevent SPI from claiming any CS lines, particularly with spidev which doesn't pass in the SPI_NO_CS flag at creation. Use the presence of an empty cs-gpios property as an indication that no CS lines should be used, bypassing the native CS conversion code. See: raspberrypi#5835 Signed-off-by: Phil Elwell <[email protected]>

Signed-off-by: Dom Cobley <[email protected]>

2712D0 has a simpler colourspace conversion matrix block so set that up. Signed-off-by: Dom Cobley <[email protected]>

2712D0 has increased the fifo sizes of MAI_THR blocks, resulting in adjusted bit offsets. Handle that. Signed-off-by: Dom Cobley <[email protected]>

…ve once vc4_hvs_dlist_free_work was iterating through the list of stale dlist entries and reading the frame count and active flags from the hardware for each one. Read the frame count and active flags once, and then use the cached value in the loop. Signed-off-by: Dave Stevenson <[email protected]>

This is largely for debug at present. For reasons unknown we are not getting the end of frame interrupts that should trigger a sweep of stale dlist entries. On allocation failure clear out ALL stale entries, and retry the allocation. Log the interrupt status so we have debug regarding whether the HVS believes the interrupt is enabled. Signed-off-by: Dave Stevenson <[email protected]>

There are three disable bits, one for each bus-instance type. Add a quirk to cover the FS/LS type, and update the slightly mangled quirk descriptions in the process. Signed-off-by: Jonathan Bell <[email protected]>

There are three parkmode disable bits, one for each bus instance type. Add FS/LS and parse the quirk out of DT. Also update the slightly mangled quirk descriptions. Signed-off-by: Jonathan Bell <[email protected]>

With the command line parser now providing the information about the tv mode, use that as the preferred choice for initialising the default of the tv_mode property. Signed-off-by: Dave Stevenson <[email protected]>

Calculate the HCNT and LCNT values for all modes using the rise and fall times of SCL, the aim being a 50/50 mark/space ratio. Signed-off-by: Phil Elwell <[email protected]>

Add support for non-standard bus speeds by treating them as detuned versions of the slowest standard speed not less than the requested speed. Signed-off-by: Phil Elwell <[email protected]>

There are multiple causes of interrupts, errors being one, and only the receipt of data warrants continued polling. See: raspberrypi#2676 Signed-off-by: Phil Elwell <[email protected]>

There is no point in trying to create a dlist entry for planes that have a 0 crtc size, and it can also cause grief in the vc6 dlist generation as it takes width-1 and height-1, causing wrap around. Drop these planes. Signed-off-by: Dave Stevenson <[email protected]>

2712D0 removed alpha_mode from control word 2 for choosing fixed alpha and replaced it with the previously reserved value of 3 in alpha_mask. Handle this to fix corrupt desktop when using X on 2712D0 Signed-off-by: Dom Cobley <[email protected]>

We have a read-modify-write race when updating SCALER_DISPCTRL for underrun and end-of-frame interrupts. Ideally it would be fixed via a spinlock or similar, but that will require a reasonable amount of study to ensure we don't get deadlocks. The underrun reporting is only for debug, so disable it for now. Signed-off-by: Dave Stevenson <[email protected]>

The code was reducing the number of components by one when we were not blending with alpha. But that only makes sense if the components include alpha. For YUV, we were reducing the number of components for Y from one to zero which resulted in no lbm space being allocated. Fixes: raspberrypi#5912 Signed-off-by: Dom Cobley <[email protected]>

If enabled, DMA_BOUNCE_UNALIGNED_KMALLOC causes the swiotlb buffers (64MB, by default) to be allocated, even on systems where the DMA controller can reach all of RAM. This is a huge amount of RAM to waste on a device with only 512MB to start with, such as the Zero 2 W. See: raspberrypi#5975 Signed-off-by: Phil Elwell <[email protected]>

This patch adds the device ID for the BCM4343A2 module, found e.g. in the Infineon (Cypress) CYW43439 chip. The required firmware file is named 'BCM4343A2.hcd'. Signed-off-by: Phil Elwell <[email protected]>

PLL_AUDIO has a ternary divider (a copy of the secondary divider) and PLL_VIDEO has a primary phased output. Signed-off-by: Jonathan Bell <[email protected]>

Add ALSA jack detection to the vc4-hdmi audio driver so userspace knows when to add/remove HDMI audio devices. Signed-off-by: David Turner <[email protected]>

The newer Raspberry Pi 5" and 7" panels have a slightly different register map to the original one. Add a new driver for this regulator. Signed-off-by: Dave Stevenson <[email protected]>

i2c_mux_add_adapter takes a force_nr parameter that allows an explicit bus number to be associated with a channel. However, only i2c-mux-reg and i2c-mux-gpio make use of it. To help with situations where it is desirable to have a fixed, known base address for the channels of a mux, create a "base-nr" property. When force_nr is 0 and base-nr is set and non-zero, form a force_nr value from the sum of base-nr and the channel ID. Signed-off-by: Phil Elwell <[email protected]>

In deep sleep mode (DS1) ARM is off and once exit trigger comes than mailbox Interrupt comes to host and whole reinitiation should be done in the ARM to start TX/RX. Also fix below issus for DS1 exit: 1. Sent Tx Control frame only after firmware redownload complete (check F2 Ready before sending Tx Control frame to Firmware) 2. intermittent High DS1 TX Exit latency time (almost 3sec) ==> This is fixed by skipping host Mailbox interrupt Multiple times (ulp state mechanism) 3. RX GlOM save/restore in Firmware 4. Add ULP event enable & event_msgs_ext iovar configuration in FMAC 5. Add ULP_EVENT_RECV state machine for sbwad support 6. Support 2 Byte Shared memory read for DS1 Exit HUDI implementation Signed-off-by: Praveen Babu C <[email protected]> Signed-off-by: Naveen Gupta <[email protected]> [Merge from 4.14.77 to 5.4.18; set BRCMF_SDIO_MAX_ACCESS_ERRORS to 20] Signed-off-by: Chi-hsien Lin <[email protected]> JIRA: SWWLAN-135583 JIRA: SWWLAN-136577

1. If firmware supports 4-way handshake offload but not supports DPP 4-way offload, when user first connects encryption network, driver will set "sup_wpa 1" to firmware, but it will further result in DPP connection failure since firmware won't send EAPOL frame to host. 2. Fix DPP AP mode handling action frames. 3. For some firmware without fwsup support, the join procedure will be skipped due to "sup_wpa" iovar returning not-support. Check the fwsup feature before do such iovar. Signed-off-by: Kurt Lee <[email protected]> Signed-off-by: Double Lo <[email protected]> Signed-off-by: Chi-hsien Lin <[email protected]>

Firmware has SME functionality but would like the userspace to handle SAE authentication. This patch adds support for such an external SAE authentication mechanism in station mode. Signed-off-by: Chung-Hsien Hsu <[email protected]> Signed-off-by: Chi-hsien Lin <[email protected]>

Commit 7d239fb broke 802.1X authentication by setting profile->use_fwsup = NONE whenever PSK is not used. However 802.1X does not use PSK and requires profile->use_fwsup set to 1X, or brcmf_cfg80211_set_pmk() fails. Fix this by checking that profile->use_fwsup is not already set to 1X and avoid setting it to NONE in that case. Fixes: 7d239fb (brcmfmac: Fix interoperating DPP and other encryption network access) Fixes: raspberrypi#5964

See commit 511ce37 ("mmc: Add MMC host software queue support") Introduced in 5.8, this feature lets the block layer issue up to 2 pending requests to the MMC layer which in certain cases can improve throughput, but in the case of this driver can significantly reduce context switching when performing random reads. On bcm2837 with a performant class A1 card, context switches under FIO random 4k reads go from ~8800 per second to ~5800, with a reduction in hardIRQs per second from ~5800 to ~4000. There is no appreciable difference in throughput. For bcm2835, and for workloads other than random read, HSQ is a wash in terms of throughput and CPU load. So, use it by default. Signed-off-by: Jonathan Bell <[email protected]>

Application class A2 cards require CQ to be enabled to realise their stated performance figures. Add support to enable/disable card CQ via the Performance Enhancement extension register, and cater for the slight differences in command set versus eMMC. Signed-off-by: Jonathan Bell <[email protected]>

The Performance Extension register is regularly accessed in a hot path to do write cache flushes. Don't invoke kmalloc/kfree for every access, preallocate a 512B buffer for this purpose. Also remove an unused alloc in sd_enable_cache(). Signed-off-by: Jonathan Bell <[email protected]>

Add a LED_FULL trigger equivalent to mmc_start_request() in mmc_cqe_start_req(), otherwise it stays off forever. Signed-off-by: Jonathan Bell <[email protected]>

For unknown reasons the controller seems to reset the idle polling timer interval on CQE enable/disable to 8 clocks which is extremely short. Just use the reset value in the eMMC spec (4096 clock periods which at 200MHz is ~20uS). Signed-off-by: Jonathan Bell <[email protected]>

The default was to have enable_bg_fill disabled and the first plane set it if it wasn't opaque and covering the whole screen. However that meant that if no planes were enabled, then the background fill wasn't enabled, and would give a striped output from the uninitialised output buffer. Initialise it to enabled to avoid this. Signed-off-by: Dave Stevenson <[email protected]>

The eMMC spec says that in certain circumstances the controller can't respond to a halt request - in practice, this occurs if a CMD timeout happens (card went away/crashed). Clear the halt request by writing 0 to CQHCI_CTL. Also fix a logic error testing for halt in cqhci_request. Signed-off-by: Jonathan Bell <[email protected]>

Certain status bits in these registers may need polling outside of SD-specific code. Export in sd_ops.h Signed-off-by: Jonathan Bell <[email protected]>

Don't attempt to turn on CQ if the other mandatory features are not indicated as supported by the card. Also make sure that the register write actually stuck, as some cards claim support but never report back that the queue engine is enabled. Signed-off-by: Jonathan Bell <[email protected]>

Also report the card's supported queue depth in the message log. Signed-off-by: Jonathan Bell <[email protected]>

The spec allows for up to two 512-byte pages to be allocated for the Extension Register General Info block, so allocate accordingly. Signed-off-by: Jonathan Bell <[email protected]>

The attached PHY performs parameter validation, so the switch from HS200 to HS (before selecting HS400/HS400es) with a 200MHz clock fails to update pad timings and results in CRC errors from the card. Underclocking the interface is safe, so do that in the downgrade callback. Signed-off-by: Jonathan Bell <[email protected]>

This gains about 8-12% sequential write speed with the fastest SD/eMMC cards, and Class A1/A2 card sequential performance is only assured with a 4MiB write length. Signed-off-by: Jonathan Bell <[email protected]>

If the controller is being reset, then the CQE needs to be reset as well. For removable cards, CQHCI_SSC1 must specify a polling mode (CBC=0) otherwise it's possible that the controller stops emitting periodic CMD13s on card removal, without raising an error status interrupt. Signed-off-by: Jonathan Bell <[email protected]>

Recovery claims the MMC card so the card-detect work gets significantly delayed - leading to lots of error recovery loops that can never do anything but fail. Explicitly detect the card after CQE has halted and bail if it's not there. Also ratelimit a not-very-descriptive warning - one occurrence in dmesg is enough to signal that something is amiss. Signed-off-by: Jonathan Bell <[email protected]>

Command Queueing requires Write Cache and Power off Notification support from the card - but using the write cache forms a contract with the host whereby the card expects to be told about impending power-down. The implication is that (for performance) the card can do unsafe things with pending write data - including reordering what gets committed to nonvolatile storage at what time. Exposed SD slots and platforms powered by hotpluggable means (i.e. Raspberry Pis) can't guarantee that surprise removal won't happen. To limit the scope for cards to invent new ways to trash filesystems, limit pending writes to 1 (equivalent to the non-CQ behaviour). Signed-off-by: Jonathan Bell <[email protected]> fixup: mmc: restrict posted write counts for SD cards in CQ mode Leaving card->max_posted_writes unintialised was a bad thing to do. Also, cqe_enable is 1 if hsq is enabled as hsq substitutes the cqhci implementation with its own. Signed-off-by: Jonathan Bell <[email protected]>

Posted write tracking introduced in the commit below raced with re-use of the requests between completion and submission, potentially causing underflow of the pending write count. Fixes: e6c1e86 ("mmc: restrict posted write counts for SD cards in CQ mode") Signed-off-by: Jonathan Bell <[email protected]>

Samsung EVO Plus, Pro Plus and Evo Ultimate cards of this era appear to have a broken cache-flush implementation when operating in CQ mode. Unfortunately the cards seem to use a separate CID name string for every variant and capacity, so nobble the cache feature for this MANFID, OEMID and year. Turning this off seems to have negligible impact on random-write throughput in non-CQ mode. Signed-off-by: Jonathan Bell <[email protected]>

Cards with manufacture dates in 2019 and 2020 have been seen in the wild that hang indefinitely if issued a cache flush command in CQ mode. Signed-off-by: Jonathan Bell <[email protected]>

Only CMD38 with Arg=0x1 (Discard) is supported when in CQ mode, so turn it off before issuing a non-discard erase op. Signed-off-by: Jonathan Bell <[email protected]>

Recent Integral cards end up with corrupt sectors after a flash erase. This covers sizes for the A2 range, which can't be differentiated from the A1 range which might not have the same issue. Signed-off-by: Jonathan Bell <[email protected]>

Newer versions of the DesignWare I2C block support the detection of stuck signals, and a mechanism to recover from them. Add the required software support to the driver. This change was prompted by the observation that reading a single byte from register 0 of a VEML7700 seems to cause it to issue an ACK too early, and the controller to complain about losing arbitration. There is a suspicion that this may be a more widespread problem, but at least this patch prevents the bus from locking up. See: raspberrypi#6057 Signed-off-by: Phil Elwell <[email protected]>

In the absence of a value in Device Tree, set the SDA hold time to half the SCL low time. Signed-off-by: Phil Elwell <[email protected]>

This supports reading and writing OTP using the firmware mailbox interface. It needs supporting firmware to run. Signed-off-by: Dom Cobley <[email protected]>

CI builds are done with debug info disabled, but this removes some members from struct module. This causes builds to fail if there is an ABI reference for the current ABI. Define these members unconditionally, so that there is no ABI change.

The legacy stack had an option to have a GPIO track frame start and end events to give basic synchronisation to the incoming image stream. https://forums.raspberrypi.com/viewtopic.php?t=190314 Replicate this in the kernel Unicam driver. Signed-off-by: Dave Stevenson <[email protected]>

This code: for_each_sg(sgl, sg, sg_len, i) num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); determines how many hw_desc are allocated. If sg_dma_len(sg)=0 we don't allocate for this sgl. However in the next loop, we will increment loop for this case, and loop gets higher than num_sgs and we trample memory. Signed-off-by: Dom Cobley <[email protected]>

The 8-bit and 16-bit mono formats were missing the appropriate remap entries in the format table. Signed-off-by: Naushir Patuck <[email protected]>

The intention of the vc4.force_hotplug setting is to ignore hotplug completely. It can be used when a display toggles hotplug when switching AV inputs, going into standby or changing a KVM switch, and some side effect of that is unwanted. It turns out while vc4.force_hotplug currently makes hotplug always read as asserted, that isn't enough to stop drm doing lots of stuff, including re-reading the edid. An example of what drm does with a hotplug deasert/assert and vc4.force_hotplug=1 currently is: https://paste.debian.net/hidden/dc07434b/ That is unwanted. Lets ignore the hotplug interrupt completely so drm is blissfully unaware of the hotplug change. Signed-off-by: Dom Cobley <[email protected]>

"rotation" is listed as a standard property of panels in panel-common.yaml, therefore it would be logical to process that from within the core code should a panel driver not implement the get_orientation hook. Call of_drm_get_panel_orientation from drm_connector_set_orientation_from_panel to get that information. This removes the need for any boiler-plate in panel drivers for calling drm_connector_set_orientation_from_panel or drm_connector_set_panel_orientation. Signed-off-by: Dave Stevenson <[email protected]>

The autodetection of resolution/timing by the TC358762 can lead to the display being shifted by a pixel or two. Program the TC358762 with the requested mode timing so that it can reproduce it accurately. Signed-off-by: Dave Stevenson <[email protected]>

Reverts 8a4b2fc ("drm/bridge: tc358762: Split register programming from pre-enable to enable") as we want the config commands sent before video starts. Signed-off-by: Dave Stevenson <[email protected]>

The initialisation sequence differs slightly from the documentation in that the clocks are meant to be running before resets and similar. Signed-off-by: Dave Stevenson <[email protected]>

vc4_dsi_bridge_disable wasn't resetting things during shutdown, so add that in. Signed-off-by: Dave Stevenson <[email protected]>

The block must be enabled for the FIFO resets to be actioned, so ensure this is the case. Signed-off-by: Dave Stevenson <[email protected]>

DSI0 is misbehaving and needs to action things on vblank to work around it. Add a new hook to call across during vblank. Signed-off-by: Dave Stevenson <[email protected]>

The pixel to byte FIFO appears to not always reset correctly, which can lead to colour errors and/or horizontal shifts. Reset on every vblank to work around the issue. Signed-off-by: Dave Stevenson <[email protected]>

The TC358762 bridge and panel decodes the mode differently on DSI0 to DSI1 for no obvious reason, and results in a shift off the screen. Whilst it would be possible to change the compatible used for the panel, that then messes up Pi5. As it appears to be restricted to vc4 DSI0, fix up the mode in vc4_dsi. Signed-off-by: Dave Stevenson <[email protected]>

Having accepted the upstream change to add the persist_gpio_outputs parameter, make it true by default. See: raspberrypi#6117 Signed-off-by: Phil Elwell <[email protected]>

vc4_disable_vblank assumed that vc4_encoder was always assigned, which isn't guaranteed. If it isn't assigned then disable the interrupt anyway as it's not connected. raspberrypi#6146 Fixes: 63c0bcc ("drm/vc4: Add option to call from crtc to encoder on vblank") Signed-off-by: Dave Stevenson <[email protected]>

Even when configured to use only gpiod CS lines, the DW SPI controller still expects a bit to be set in the SER register, otherwise transfers stall. For the csgpiod case, nominate bit 0 for the job. See: raspberrypi#6159 Signed-off-by: Phil Elwell <[email protected]>

Add shutdown and remove hooks so that the panel gets powered off with the system. Signed-off-by: Dave Stevenson <[email protected]>

As with many microcontrollers, the panel wants to use clock stretching during a read so that the appropriate return value can be generated and programmed into the hardware. With Pi0-3 really not supporting clock stretching, this resulted in the panel firmware dying. Insert a delay between the write and the read to give the firmware a chance to generate the relevant return value. Signed-off-by: Dave Stevenson <[email protected]>

There are no MEDIA_BUS_FMT_* defines for GRB or BRG, and adding them is a pain. Add a DT override to allow setting the order. Signed-off-by: Dave Stevenson <[email protected]>

The naming of backlight devices is not terribly useful for associating a backlight controller with a display (assuming it is attached to one). Add a sysfs node that will return a display name that can be set by other subsystems. Signed-off-by: Dave Stevenson <[email protected]>

Pass the DRM connector name to any configured backlight device so that userspace can associate the two items. Ideally this should be in drm_panel, but it is bridge/panel that creates the drm_connector and therefore knows the name. Signed-off-by: Dave Stevenson <[email protected]> drm/bridge: panel: Ensure backlight is reachable Ensure that the various options of modules vs builtin results in being able to call into the backlight code. raspberrypi#6198 Fixes: 573f8fd ("drm/bridge: panel: Name an associated backlight device") Signed-off-by: Dave Stevenson <[email protected]>

Add version 4.17.1 of the Hailo PCIe device drivers. Sourced from https://github.com/hailo-ai/hailort-drivers/ Signed-off-by: Naushir Patuck <[email protected]>

An attempt to fix the include paths - they look reasonable, but the GitHub auto-builds fail. Signed-off-by: Phil Elwell <[email protected]>

Sourced from https://github.com/hailo-ai/hailort-drivers/ Signed-off-by: Naushir Patuck <[email protected]>

Signed-off-by: Phil Elwell <[email protected]>

Add helpers to set and get vchiq driver data. vchiq_set_drvdata() and vchiq_get_drvdata() wraps dev_set_drvdata() and dev_get_drvdata() respectively. Signed-off-by: Umang Jain <[email protected]> Signed-off-by: Kieran Bingham <[email protected]>

The vchiq_connected.h header was removed in f875976 ("staging: vc04_services: Drop vchiq_connected.[ch] files") to simplify the implementation. Update the vc_sm driver accordingly which can still use the same functions through the vchiq_arm.h header declarations. Fixes: b1ab7a0 ("staging: vc04_services: Add new vc-sm-cma driver") Signed-off-by: Kieran Bingham <[email protected]>

Drop the include directive. They can break the build, when one only wants to build a subdirectory. Replace with "../" for the includes in the vc_sm files instead. The fix is equivalent to the four patches between 29d49a7 ("staging: vc04_services: bcm2835-audio: Drop include Makefile directive")...2529ca2 ("staging: vc04_services: interface: Drop include Makefile directive") Fixes: b1ab7a0 ("staging: vc04_services: Add new vc-sm-cma driver") Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Kieran Bingham <[email protected]>

Register the vcsm rive with the vchiq_bus_type instead of useing the platform driver/device. Signed-off-by: Kieran Bingham <[email protected]>

Signed-off-by: Phil Elwell <[email protected]>

After the decision to use bcm2711 compatible for upstream, we should switch all accepted compatibles to bcm2711. So we can boot with one DTB the down- and the upstream kernel. Signed-off-by: Stefan Wahren <[email protected]>

Now that V4L2_PIX_FMT_Y12P is defined, allow passing raw 12bit mono packed data through the peripheral. Signed-off-by: Dave Stevenson <[email protected]>

Now that V4L2_PIX_FMT_Y14 and V4L2_PIX_FMT_Y14P are defined, allow passing 14bit mono data through the peripheral. Signed-off-by: Dave Stevenson <[email protected]>

Now that the 14bit non-packed Bayer formats are defined, add them into the supported formats lookup table. Signed-off-by: Dave Stevenson <[email protected]>

Polarity bits were only ever set and never cleared. Make sure they can also be cleared. Signed-off-by: Michiel Vanbiervliet <[email protected]>

Add two new DT properties: * microchip,eee-enabled - a boolean to enable EEE * microchip,tx-lpi-timer - time in microseconds to wait before entering low power state Signed-off-by: Phil Elwell <[email protected]>

Disabling tx_lpi or eee should not cause the value of tx_lpi_timer to be lost, even though it is not useful until they are re-enabled. Signed-off-by: Phil Elwell <[email protected]>

The platform model originally handled the DMA mask. Now that we are on the vchiq_bus we need to explicitly set this. Signed-off-by: Kieran Bingham <[email protected]>

Backport to rpi-6.6.y the mainline version of the PiSP BE driver. The backported version of the driver corresponds to the one available at: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Jacopo Mondi <[email protected]>

Re-introduce multi-context support that was dropped from the mainline driver version. Signed-off-by: Jacopo Mondi <[email protected]>

Offset the backend dev-nodes starting at /dev/video20 onwards to maintain backward compatibility with the pre-upstreamed kernel driver. Signed-off-by: Naushir Patuck <[email protected]>

Add YAML device tree bindings for the Raspberry Pi RP2040 GPIO Bridge. Signed-off-by: Richard Oliver <[email protected]>

The Raspberry Pi RP2040 GPIO bridge is an I2C-attached device exposing both a Tx-only SPI controller, and a GPIO controller. Due to the relative difference in transfer rates between standard-mode I2C and SPI, the GPIO bridge makes use of 12 MiB of non-volatile storage to cache repeated transfers. This cache is arranged in ~8 KiB blocks and is addressed by the MD5 digest of the data contained therein. Optionally, this driver is able to take advantage of Raspberry Pi RP1 GPIOs to achieve faster than I2C data transfer rates. Signed-off-by: Richard Oliver <[email protected]> spi: rp2040-gpio-bridge: Add debugfs progress indicator Useful for tracking upload progress via userspace. Signed-off-by: Naushir Patuck <[email protected]> spi: rp2040-gpio-bridge: add missing MD5 dependency rp2040-gpio-bridge relies on the md5 crypto driver. This dependency cannot be determined automatically as rp2040-gpio-bridge does not use any of md5's symbols directly. Declare a soft 'pre' dependency on md5 to ensure that it is included and loaded before rp2040-gpio-bridge. Signed-off-by: Richard Oliver <[email protected]>

The snps,block-size DT property declares the maximum block size for each channel of the dw-axi-dmac. However, the driver ignores these when setting max_seg_size and uses MAX_BLOCK_SIZE (4096) instead. To take advantage of the efficiencies of larger blocks, calculate the minimum block size across all channels and use that instead. See: raspberrypi#6256 Signed-off-by: Phil Elwell <[email protected]>

The firmware advertises its features as a string of words separated by spaces. Ensure that feature names are only matched in their entirety. Signed-off-by: Phil Elwell <[email protected]>

The Cypress firmwares use "extsae" to indicate wpa_supplicant-hosted SAE/WPA3. Signed-off-by: Phil Elwell <[email protected]>

support sae executed in wpa_supplicant and offload 4-way handshake offload. Signed-off-by: Chien-Chia Chen <[email protected]> JIRA: SWWLAN-142424

Define two new RP1 clocks, representing the MIPI DSI byteclock sources for the dividers used to generate MIPI[01] DPI pixel clocks. (Previously they were represented by "fake" fixed clocks sources). Signed-off-by: Nick Hollinghurst <[email protected]>

Whilst the Unicam driver has now been upstreamed it only supports configuration via Media Controller (not driven from the /dev/videoN node), which makes life significantly harder for simple devices such as mono sensors, and HDMI or analogue video to CSI2 bridge chips (eg TC358743 and ADV7282M). Fix up the downstream driver so that it builds, reinstate the links from Kconfig and Makefile to it, and give it a new Kconfig name (VIDEO_BCM2835_UNICAM_LEGACY). Signed-off-by: Dave Stevenson <[email protected]>

The upstream Unicam driver needs a set of userland changes to get libcamera to run, and those aren't written or merged yet. Move the "brcm,bcm2835-unicam" compatible from the upstream driver to the old downstream version so that users can run libcamera against 6.10. Once the libcamera changes have been merged this can be reverted to use the upstream driver. If using the non-legacy compatible then assume we want to use media-controller API for configuration. Signed-off-by: Dave Stevenson <[email protected]>

Automatic link power saving plus the ability of a root complex to buffer pending posted write transfers (and consider them complete before being transmitted on the wire) causes compression of updates to GPIO state. The large bandwidth of a Gen 2 x4 link means the writes toggle state inside RP1 as fast as it can go (~20MHz), which is bad for applications wanting bitbash with at least a few microseconds of delay between updates. By tailoring IO access patterns to a special Root Complex register, writes to GPIOs can be stalled until the link wakes - meaning all writes end up with a reasonably consistent minimum pacing (~200ns). Additionally, write barriers have no effect other than to arbitrarily delay some writes by a small, variable amount - so remove the vast majority of these in areas that could be hot-paths. Although the IO memory is mapped with Device strongly-ordered semantics, this doesn't prevent the splitter inside BCM2712 from letting an MMIO read request to a GPIO register get ahead of the pacing writes to the Root Complex register. So each pin state read must flush writes out to the Outer-Shareable domain. Signed-off-by: Jonathan Bell <[email protected]>

TMOD_TO is the transmit-only mode that doesn't put data into the receive FIFO. Using TMOD_TO when the user doesn't want the received data saves CPU time and memory bandwidth. Signed-off-by: Phil Elwell <[email protected]>

TMOD_RO is the receive-only mode that doesn't require data in the transmit FIFO in order to generate clock cycles. Using TMOD_RO when the device doesn't care about the data sent to it saves CPU time and memory bandwidth. Signed-off-by: Phil Elwell <[email protected]>

Disabling the peripheral resets controller state which has a dangerous side-effect of disabling the DMA handshake interface while it is active. This can cause DMA channels to hang. The error recovery pathway will wait for DMA to stop and reset the chip anyway, so mask further FIFO interrupts and let the transfer finish gracefully. Signed-off-by: Jonathan Bell <[email protected]>

There's no real need to constrain MEM access widths to 32-bit (or narrower), as the DMAC is intelligent enough to size memory accesses appropriately. Wider accesses are more efficient. Similarly, MEM burst lengths don't need to be a function of DEV burst lengths - the DMAC packs/unpacks data into/from its internal channel FIFOs appropriately. Longer accesses are more efficient. However, the DMAC doesn't have complete support for unaligned accesses, and blocks are always defined in integer multiples of SRC_WIDTH, so odd source lengths or buffer alignments will prevent wide accesses being used, as before. There is an implicit requirement to limit requested DEV read burst lengths to less than the hardware's maximum configured MSIZE - otherwise RX data will be left over at the end of a block. There is no config register that reports this value, so the AXI burst length parameter is used to produce a facsimile of it. Warn if such a request arrives that doesn't respect this. Signed-off-by: Jonathan Bell <[email protected]>

Do an end-run around ASoC in lieu of not being able to easily find the associated DMA controller capabilities. Signed-off-by: Jonathan Bell <[email protected]>

…ints Valid ranges for the I2S peripheral's FIFO configuration include a depth of 16 - unconditionally setting the burst length to 16 with a fifo threshold of size/2 will cause under/overflows. For DMA engines with restricted capabilities the requested burst length and FIFO thresholds need to be adjusted downward accordingly. Both the RX and TX FIFOs operate on "less-than" thresholds. Setting the TX threshold to fifo_size minus burst means the FIFO is kept nearly-full. Signed-off-by: Jonathan Bell <[email protected]>

Pi 0-3 have no deep colour support and only 24bpp output, so max_bpc should remain as 8. Signed-off-by: Dave Stevenson <[email protected]>

Ensure the transmit FIFO has emptied before ending the transfer by dropping the TX threshold to 0 when the last byte has been pushed into the FIFO. Include a similar fix for the non-IRQ paths. See: raspberrypi#6285 Fixes: 6014649 ("spi: dw: Save bandwidth with the TMOD_TO feature") Signed-off-by: Phil Elwell <[email protected]>

The DW SPI interface has a 16-bit clock divider, where the bottom bit of the divisor must be 0. Limit how low the clock speed can go to prevent the clock divider from being truncated, as that could lead to a much higher clock rate than requested. Signed-off-by: Phil Elwell <[email protected]>

Signed-off-by: Phil Elwell <[email protected]>

In the same way that other subsystems support the setting of device id numbers from Device Tree aliases, allow gpiochip numbers to be derived from "gpiochip<n>" aliases. Signed-off-by: Phil Elwell <[email protected]>

Get the KUnit tests passing. Signed-off-by: Maíra Canal <[email protected]>

Although later functions can handle a NULL fwnode, fwnode can't handle being passed a NULL pointer. See: raspberrypi#6305 Signed-off-by: Phil Elwell <[email protected]>

There appears to be a requirement for some devices (I'm testing with a 8K VRROOM 40Gbps HDMI switch) for a measable delay between removing the hdmi phy output from the old mode, to enabling the hdmi phy output for the new mode. Without the delay, a mode switch has a small change of getting a permanent 'no signal', which requires a subsequent mode switch or a unplug/replug to redetect. Switching between 4kp24/25/30 modes fails about 5% of time in my testing. Add a delay to make it impossible to switch faster than this. Signed-off-by: Dom Cobley <[email protected]>

The body of this function was missing so we don't reset the phy when disabling it. Signed-off-by: Dom Cobley <[email protected]>

The current reset code doesn't actually stop the hdmi output. That makes it difficult for displays to handle a mode set. Powering down the PLL does actually remove the hdmi signal and makes mode sets more reliable Signed-off-by: Dom Cobley <[email protected]>

The check if the oscillator stop bit is set was reading from Control_1 register instead of the Seconds register. This caused the Seconds register to be incorrectly changed if bit 7 of Control_1 happens to be set. Signed-off-by: Axel Hammarberg <[email protected]>

Add YAML device tree binding for the Sony IMX500 CMOS image sensor / CNN inference engine. Also, add a MAINTAINERS entry. Signed-off-by: Richard Oliver <[email protected]>

The Sony IMX500 is a stacked 1/2.3-inch CMOS digital image sensor and inbuilt AI processor with an active array CNN (Convolutional Neural Network) inference engine. The native sensor size is 4056H x 3040V, and the module also contains an in-built ISP for the CNN. The module is programmable through an I2C interface with firmware and neural network uploads being made over SPI. This driver supports imaging only. Signed-off-by: Richard Oliver <[email protected]> media: i2c: imx500: Inbuilt AI processor support Add support for the IMX500's inbuilt AI processor. The IMX500 program loader, AI processor firmware, DNN weights are accessed via the kernel's firmware interface on 'open' and are transferred to the IMX500 over SPI. Signed-off-by: Richard Oliver <[email protected]> media: i2c: imx500: Enable LED during SPI transfers The Raspberry Pi 'AI Camera' is equipped with an LED. Enable this LED during SPI transfers to indicate to the end-user that progress is being made during large tramsfers. Signed-off-by: Richard Oliver <[email protected]> drivers: media: imx500: Fixes for vblank control Reduce the default/max framerate of the 2x2 binned mode to 30fps. The current limit of 50fps can cause the sensor to produce corrupt frames and cause missing framing events. Also fixup the vblank control min/max/default/step paramters when setting up. Signed-off-by: Naushir Patuck <[email protected]> drivers: media: imx500: Simplify the vblank control init Set the VBLANK control minimum and default values to IMX500_VBLANK_MIN unconditionally everywhere. Remove the mode specific framerate_default parameter, it is now unused. Signed-off-by: Naushir Patuck <[email protected]>

Add EXPORT_SYMBOL_GPL() for find_cpio_data() so that loadable modules may also parse uncompressed cpio. Signed-off-by: Richard Oliver <[email protected]>

The driver did expose V4L2_CID_HBLANK, but as a READ_ONLY control. The sensor only uses the HTS register to control the line length, so convert this control to read/write, with the appropriate ranges. Adopt the old fixed values as the minimum values permitted in each mode to avoid issues of it not streaming. This should allow exposure times up to ~3 seconds (up from ~1sec). Signed-off-by: Dave Stevenson <[email protected]>

Seeing as the HVS can be configured with regard the scaling filter, and DRM now supports selecting scaling filters at a per CRTC or per plane level, we can implement it. Default remains as the Mitchell/Netravali filter, but nearest neighbour is now also implemented. Signed-off-by: Dave Stevenson <[email protected]> drm: vc4: Fix interpolate bit for nearest neighbour filter Operator precedence resulted in the wrong value being written for nearest neighbour mode. Correct it. Fixes: d6a3a3f ("drm/vc4: Add support for per plane scaling filter selection") Signed-off-by: Dave Stevenson <[email protected]>

ili9881c_enable is always returning 0. ili9881c_disable was returning the error code from mipi_dsi_dcs_set_display_off. If non-zero, the drm_panel framework will leave the panel marked as enabled, and not run the enable hook next time around. That isn't helpful, particularly as we're expecting unprepare to disable resets and regulators. Change ili9881c_disable to match enable in always returning 0. Signed-off-by: Dave Stevenson <[email protected]>

Some DSI peripheral drivers wish to send commands in the post_disable or panel unprepare callback. These are called after the DSI host's disable call, but before the host's post_disable if pre_enable_prev_first is set. Don't reset the block until post_disable to allow these commands to be sent. Signed-off-by: Dave Stevenson <[email protected]>

The DSI block appears to be able to come up stuck in a condition where it leaves the lanes in HS mode or just jabbering. This stops LP transfers from completing as there is no LP time available. This is signalled via the LP1 contention error. Enabling video briefly clears that condition, so if we detect the error condition, enable video mode and then retry. Signed-off-by: Dave Stevenson <[email protected]>

The driver is typically asking for LP commands, but then tries to send set_display_[on|off] from enable/disable when the host will be in HS mode. It also sends shutdown commands just before it asserts reset and disables the regulator, which is rather redundant. Add an option to configure these two choices from the panel_desc. Signed-off-by: Dave Stevenson <[email protected]>

Since we don't use the (absent) SMI block to create interrupts on BCM2712, there's no need to map any registers. Signed-off-by: Phil Elwell <[email protected]>

The previous UPM allocation was done per plane state, when there is no overlap of usage between frames. Allocate per plane, and only change the allocation if the required size changes. We have to reference count as plane states can be duplicated. Signed-off-by: Dave Stevenson <[email protected]>

LBM is only relevant for each active dlist, so there is no need to double-buffer the allocations. Cache the allocations per plane so that we can ensure the allocations are possible. Signed-off-by: Dave Stevenson <[email protected]>

Seeing as it is userspace that creates the state and commit that is validated, drop the log messages to debug to avoid userspace being able to totally spam the kernel log. Signed-off-by: Dave Stevenson <[email protected]>

This correction is calibrated to approx 5000K. Signed-off-by: Naushir Patuck <[email protected]>

The USER_LED signal was missing from the initial DTS. Signed-off-by: Phil Elwell <[email protected]>

This works and can be useful for debugging/benchmarking/low power use $ nproc 4 $ echo 0 | sudo tee /sys/devices/system/cpu/cpu3/online 0 $ echo 0 | sudo tee /sys/devices/system/cpu/cpu2/online 0 $ echo 0 | sudo tee /sys/devices/system/cpu/cpu1/online 0 $ nproc 1 Signed-off-by: Dom Cobley <[email protected]>

@n

The overlay was creating DT nodes /clocks/clk-aicam and /clocks/clk-aicam-gated for both cam0 and cam1, which resulted in one failing. The clock infrastructure creates the clock name from the node name without any @n reg extension, so we can't just use that. The nodes therefore have to be renamed. Signed-off-by: Dave Stevenson <[email protected]>

It tried to be a clone of the Pi 7" display, but isn't, and gives corrupt images with the current timings. Add a new overlay for it. Signed-off-by: Dave Stevenson <[email protected]>

Currently, booting with no hdmi connected has: pi@pi4:~ $ vcgencmd measure_clock hdmi pixel frequency(9)=120010256 frequency(29)=74988280 After connecting hdmi we get: pi@pi4:~ $ vcgencmd measure_clock hdmi pixel frequency(9)=300005856 frequency(29)=149989744 and that persists after disconnecting hdmi I can measure this on a power supply as [email protected] (52mW). We should always remove clk_set_min_rate requests when we no longer need them. Signed-off-by: Dom Cobley <[email protected]>

Older Pis arrange that the camera I2C ports appear as /dev/i2c-10. Add aliases so that on the Pi 5 family, i2c_csi_dsi0 becomes i2c-10 and i2c_csi_dsi1 becomes i2c-11. Only the I2C buses that appear on the 40-pin header, i.e. I2C0 to I2C3, get a low bus number. Also add hints for our udev rules about which symlinks to create for backwards-compatibility with the previous bus numbers. Note that lower numbers have priority, so i2c-0 on CM5 masks i2c-11, forcing i2c-11 to be a symlink to i2c-0, not vice versa. Signed-off-by: Phil Elwell <[email protected]>

The i.MX8MP makes calls on it's source device to determine the link-frequency that should be configured on the CSI2 receiver. When the source is behind a video mux, we need to pass this call through to the connected device. Map the control handler of the source device to the video-mux, essentially proxying all controls on the mux to the device which has it's link enabled. Signed-off-by: Kieran Bingham <[email protected]>

The current order of locking between the driver mutex and the v4l2 subdev state lock causes a circuluar locking dependency when trying to set up a link. Fix this. Signed-off-by: Paul Elder <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Signed-off-by: Kieran Bingham <[email protected]>

To make comparisons of the mode registers easier, put the registers for the binned and VGA modes in the same order as the others. Signed-off-by: Dave Stevenson <[email protected]>

There are many registers in common between all the modes. Pull those out into one common table. Signed-off-by: Dave Stevenson <[email protected]>

…ed modes In order to simplify the driver slightly, use the same PLL configuration, and hence pixel rate and link frequency (to be added) for the full, 1080p, and binned modes. Signed-off-by: Dave Stevenson <[email protected]>

The link frequency can vary between modes, so add it as a control. Signed-off-by: Dave Stevenson <[email protected]>

system_heap.max_order=<uint> Signed-off-by: Tvrtko Ursulin <[email protected]>

Add numa_policy kernel argument to allow overriding the kernel's default NUMA policy at boot time. Syntax identical to what tmpfs accepts as it's mpol argument is accepted. Some examples: numa_policy=interleave numa_policy=interleave=skip-interleave numa_policy=bind:0-3,5,7,9-15 numa_policy=bind=static:1-2 Signed-off-by: Tvrtko Ursulin <[email protected]>

... Make sure CMA zones do not straddle the emulated NUMA nodes ... Signed-off-by: Tvrtko Ursulin <[email protected]>

Allow NUMA and NUMA_EMULATION on 64-bit Pi kernels Signed-off-by: Dom Cobley <[email protected]>

Most 2711 devices and all 2712 device share common bootargs (command lines). Make the common values shared defaults, overriding them were necessary. Signed-off-by: Phil Elwell <[email protected]>

The default cmdline adjustment is now numa_policy=interleave for 2711 and 2712, and additionally system_heap.max_order=0 iommu_dma_numa_policy=interleave for just 2712 (due to its better iommu support). The key setting numa=fake=<n> is not set here, so we will boot with a single numa region and behaviour should be pretty much unchanged from before this PR. Signed-off-by: Dom Cobley <[email protected]>

The transposer/writeback connector should be running with a lower priority, so shouldn't be factored into the load calculations. Signed-off-by: Dave Stevenson <[email protected]>

As the writeback connector doesn't have the same realtime constraints of a live display, drop the panic priority for it. Signed-off-by: Dave Stevenson <[email protected]>

Reduce the number of different places that bootargs is set in Pi dts files. The variants are all combinations of with/without Bluetooth and with/without NUMA support (2711). This is effectively a cosmetic change - the resulting dtbs are unchanged. Signed-off-by: Phil Elwell <[email protected]>

Commit 94a23e9 ("cgroup: Disable cgroup "memory" by default") disabled the memory cgroup by default when initing the cgroups. However, it's possible to disable the memory cgroup by a kernel command line. Hard-coding such a feature can be problematic as some memory management features depend on the order that things are set. For example, it is possible to see a NULL pointer dereference caused by commit 94a23e9. The NULL pointer dereference is triggered by the memory shrinker and ends up in a kernel crash. [ 50.028629] ================================================================== [ 50.028645] BUG: KASAN: null-ptr-deref in do_shrink_slab+0x1fc/0x978 [ 50.028663] Write of size 8 at addr 0000000000000000 by task gfxrecon-replay/1965 [ 50.028676] CPU: 3 UID: 1000 PID: 1965 Comm: gfxrecon-replay Tainted: G C 6.12.0-rc4-v8-thp-kasan+ raspberrypi#85 [ 50.028685] Tainted: [C]=CRAP [ 50.028689] Hardware name: Raspberry Pi 5 Model B Rev 1.0 (DT) [ 50.028694] Call trace: [ 50.028697] dump_backtrace+0xfc/0x120 [ 50.028706] show_stack+0x24/0x38 [ 50.028711] dump_stack_lvl+0x40/0x88 [ 50.028720] print_report+0xe4/0x708 [ 50.028728] kasan_report+0xcc/0x130 [ 50.028733] kasan_check_range+0x254/0x298 [ 50.028738] __kasan_check_write+0x20/0x30 [ 50.028745] do_shrink_slab+0x1fc/0x978 [ 50.028751] shrink_slab+0x318/0xc38 [ 50.028756] shrink_one+0x254/0x6d8 [ 50.028762] shrink_node+0x26b4/0x2848 [ 50.028767] do_try_to_free_pages+0x3e4/0x1190 [ 50.028773] try_to_free_pages+0x5a4/0xb40 [ 50.028778] __alloc_pages_direct_reclaim+0x144/0x298 [ 50.028787] __alloc_pages_slowpath+0x5c4/0xc70 [ 50.028793] __alloc_pages_noprof+0x4a8/0x6a8 [ 50.028800] __folio_alloc_noprof+0x24/0xa8 [ 50.028806] shmem_alloc_and_add_folio+0x2ec/0xce0 [ 50.028812] shmem_get_folio_gfp+0x380/0xc20 [ 50.028818] shmem_read_folio_gfp+0xe0/0x160 [ 50.028824] drm_gem_get_pages+0x238/0x620 [drm] [ 50.029039] drm_gem_shmem_get_pages_sgt+0xd8/0x4b8 [drm_shmem_helper] [ 50.029053] v3d_bo_create_finish+0x58/0x1e0 [v3d] [ 50.029083] v3d_create_bo_ioctl+0xac/0x210 [v3d] [ 50.029105] drm_ioctl_kernel+0x1d8/0x2b8 [drm] [ 50.029220] drm_ioctl+0x4b4/0x920 [drm] [ 50.029330] __arm64_sys_ioctl+0x11c/0x160 [ 50.029337] invoke_syscall+0x88/0x268 [ 50.029345] el0_svc_common+0x160/0x1d8 [ 50.029351] do_el0_svc+0x50/0x68 [ 50.029358] el0_svc+0x34/0x80 [ 50.029364] el0t_64_sync_handler+0x84/0x100 [ 50.029371] el0t_64_sync+0x190/0x198 [ 50.029376] ================================================================== This happens because the memory shrinker is unaware that we are artificially disabling the memory cgroups and therefore it doesn't allocate `nr_deferred` (as it would if we used the kernel command line). To avoid such an issue, revert the artificial disablement and disable it through the command line. If a user wants to enable the feature, it can use the `cgroup_enable=` command line. Signed-off-by: Maíra Canal <[email protected]>

There is a difference in I2C usage between CM4IO and CM5IO. Present a simple, consistent view of the world by moving the assignment of the bus IDs into carrier-specific files. CM5 has reduced connectivity on CM4IO - the DPHYs are connected to CAM1 and DISP1. Keep i2c-10 for use with that pair, as is the case for CM4 on CM4IO. Fixes: 36faab6 ("dts: bcm2712-rpi: Add aliases for the CSI/DSI I2Cs") See: raspberrypi#6421 Signed-off-by: Phil Elwell <[email protected]>

Clients such as libcamera do not change the LS table dmabuf on every frame. In such cases instead of mapping/remapping the same dmabuf on every frame to send to the firmware, cache the dmabuf once and only update and remap if the dmabuf has been changed by the userland client. Signed-off-by: Naushir Patuck <[email protected]>

Enable the PWM GPIO module in Raspberry Pi kernels. Signed-off-by: Tim Gover <[email protected]>

Signed-off-by: Tim Gover <[email protected]>

As a workaround (and possibly a fix) for CPU spins observed on BCM2837, use ptep_clear_flush_young instead of ptep_test_and_clear_young inside lru_gen_look_around in order to expose PTE changes to the MMU. Note that on architectures that don't require an explicit flush, ptep_clear_flush_young just calls ptep_test_and_clear_young. Signed-off-by: Phil Elwell <[email protected]>

iommu_dma_numa_policy=interleave is not valid in the current tree It generates an unknown setting will be passed to usespace warning system_heap.max_order=0 is wanted when numa is enabled, but may not be when it is disabled. Add it on firmware side when we know if numa=fake=<n> is used. Signed-off-by: Dom Cobley <[email protected]>

A user has reported that a card of this model from late 2021 doesn't work, so extend the date range and make it match on all card sizes. Signed-off-by: Jonathan Bell <[email protected]>

Add two quirk properties that control whether or not the controller issues many more handshakes to FS/HS Async endpoints in a single (micro)frame. Enabling these can significantly increase throughput for endpoints that frequently respond with NAKs. Signed-off-by: Jonathan Bell <[email protected]>

If a device frequently NAKs, it can exhaust the scheduled handshakes in a frame. It will then not get polled by the controller until the next frame interval. This is most noticeable on FS devices as the controller schedules a small set of transactions only once per full-speed frame. Setting the ENH_PER_NAK_FS/LS bits in the GUCTL1 register increases the number of transactions that can be scheduled to Async (Control/Bulk) endpoints in the respective frame time. In the FS case, this only applies to FS devices directly connected to root ports. Signed-off-by: Jonathan Bell <[email protected]>

There seem to be only benefits, and no downsides. Signed-off-by: Jonathan Bell <[email protected]>

For platforms that have xHCI controllers attached over PCIe, and non-coherent routes to main memory, a theoretical race exists between posting new TRBs to a ring, and writing to the doorbell register. In a contended system, write traffic from the CPU may be stalled before the memory controller, whereas the CPU to Endpoint route is separate and not likely to be contended. Similarly, the DMA route from the endpoint to main memory may be separate and uncontended. Therefore the xHCI can receive a doorbell write and find a stale view of a transfer ring. In cases where only a single TRB is ping-ponged at a time, this can cause the endpoint to not get polled at all. Adding a readl() before the write forces a round-trip transaction across PCIe, definitively serialising the CPU along the PCI producer-consumer ordering rules. Signed-off-by: Jonathan Bell <[email protected]>

The DHT11 datasheet is pretty cryptic, but it does suggest that after each integer value (humidity and temperature) there are "decimal" values. Validate these as integers in the range 0-9 and treat them as tenths of a unit. Link: raspberrypi#6220 Signed-off-by: Phil Elwell <[email protected]>

The logic for dropping a plane less than zero didn't account for the possibility that a plane could be being upscaled with a src_rect with width/height < 1 pixel, but not 0 subpixels. Check for not 0 subpixels, not < 1, in both vc4 and vc6 paths. Fixes: dac6168 ("drm/vc4: Drop planes that have 0 destination size") Fixes: f73b18e ("drm/vc4: Drop planes that are completely off-screen") Signed-off-by: Dave Stevenson <[email protected]>

The documentation says that the TPZ filter can not upscale, and requesting a scaling factor > 1:1 will output the original image in the top left, and repeat the right/bottom most pixels thereafter. That fits perfectly with upscaling a 1x1 image which is done a fair amount by some compositors to give solid colour, and it saves a large amount of LBM (TPZ is based on src size, whilst PPF is based on dest size). Select TPZ filter for images with source rectangle <=1. Signed-off-by: Dave Stevenson <[email protected]>

…ctors The non-desktop property "Indicates the output should be ignored for purposes of displaying a standard desktop environment or console." That sounds like it should be true for all writeback and virtual connectors as you shouldn't render a desktop to them, so set it by default. Signed-off-by: Dave Stevenson <[email protected]>

The limit of 32 planes per DRM device is dictated by the use of planes_mask returning a u32. Change to a u64 such that 64 planes can be supported by a device. Signed-off-by: Dave Stevenson <[email protected]>

The HVS can accept an arbitrary number of planes, provided that the overall pixel read load is within limits, and the display list can fit into the dlist memory. Now that DRM will support 64 planes per device, increase the number of overlay planes from 16 to 48 so that the dlist complexity can be increased (eg 4x4 video wall on each of 3 displays). Signed-off-by: Dave Stevenson <[email protected]>

Instead of having 48 generic overlay planes, assign 32 to the writeback connector so that there is no ambiguity in wlroots when trying to find a plane for composition using the writeback connector vs display. Signed-off-by: Dave Stevenson <[email protected]>

Some hardware will implement transpose as a rotation operation, which when combined with X and Y reflect can result in a rotation, but is a discrete operation in its own right. Add an option for transpose only. Signed-off-by: Dave Stevenson <[email protected]>

Some connectors, particularly writeback, can implement flip or transpose operations as writing back to memory. Add a connector rotation property to control this. Signed-off-by: Dave Stevenson <[email protected]>

The txp block can implement transpose as it writes out the image data, so expose that through the new connector rotation property. Signed-off-by: Dave Stevenson <[email protected]>

For devices where transfer lengths are not known upfront, there is a danger when the destination is wider than the source that partial words can be lost at the end of a transfer. Ideally the controller would be able to flush the residue, but it can't - it's not even possible to tell that there is any. Instead, allow the client driver to avoid the problem by setting a smaller width. Signed-off-by: Phil Elwell <[email protected]>

SPI transfers are of defined length, unlike some UART traffic, so it is safe to let the DMA controller choose a suitable memory width. Signed-off-by: Phil Elwell <[email protected]>

In order to avoid losing residue bytes when a receive is terminated early, set the destination width to single bytes. Link: raspberrypi#6365 Signed-off-by: Phil Elwell <[email protected]>

Historically we have booted in powersave mode, and switched to ondemand with the /etc/init.d/raspi-config scipt if the shift key is not pressed. This was intended to protect users from an unsafe overclock, or inadequate power supply. But there's little evedence that this option is benefitting anyone, and we can boot faster without it. Signed-off-by: Dom Cobley <[email protected]>

The xHC may commence Host Initiated Data Moves for streaming endpoints - see USB3.2 spec s8.12.1.4.2.4. However, this behaviour is typically counterproductive as the submission of UAS URBs in {Status, Data, Command} order and 1 outstanding IO per stream ID means the device never enters Move Data after a HIMD for Status or Data stages with the same stream ID. For OUT transfers this is especially inefficient as the host will start transmitting multiple bulk packets as a burst, all of which get NAKed by the device - wasting bandwidth. Also, some buggy UAS adapters don't properly handle the EP flow control state this creates - e.g. RTL9210. Set Host Initiated Data Move Disable to always defer stream selection to the device. xHC implementations may treat this field as "don't care, forced to 1" anyway - xHCI 1.2 s4.12.1. Signed-off-by: Jonathan Bell <[email protected]>

The commit 91f059c ("mmc: core: Capture eMMC and SD card errors") introduced MMC error stats, which are accessible via debugfs. Implement the necessary increment calls for the BCM2835 SDHOST driver, which isn't SDHCI compatible. This is useful for debug and testing. Signed-off-by: Stefan Wahren <[email protected]>

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[DO NOT MERGE] mmc: host: bcm2835: Capture MMC errors #6475

[DO NOT MERGE] mmc: host: bcm2835: Capture MMC errors #6475

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[DO NOT MERGE] mmc: host: bcm2835: Capture MMC errors #6475

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[DO NOT MERGE] mmc: host: bcm2835: Capture MMC errors #6475

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