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Full tywaves pipeline explained
Raffaele Meloni edited this page Jun 26, 2024
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The following section contains some UML diagrams showing some details of the internal execution and data structures in Tywaves.
- Fig. 1: Sequence diagram highlighting the steps in Chisel + when it calls to CIRCT, Verilator, Surfer
- Fig. 2: Sequence diagram highlighting the steps in CIRCT: TODO
- Fig. 3: Sequence diagram highlighting the loading and translation phase of typed waveforms given an input trace and hgldd directory
- Fig. 4: Class diagram of the hgldd module in Tywaves-rs
- Fig. 5: Class diagram of the tyvcd module in Tywaves-rs
Here the portion of sequence diagram highlighting the steps in Chisel.
Fig. 1: Sequence diagram highlighting the steps in Chisel + when it calls to CIRCT, Verilator, Surfer |
Here the portion of sequence diagram highlighting the steps in CIRCT.
Here the portion of sequence diagram highlighting the steps in the viewer.
Fig. 3: Sequence diagram highlighting the loading and translation phase of typed waveforms given an input trace and hgldd directory |
Fig. 4: Class diagram of the hgldd module in Tywaves-rs |
Fig. 5: Class diagram of the tyvcd module in Tywaves-rs |