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Merge pull request #43 from rameloni/42-firtool-complains-on-field-ac…
…cess Bug fix: Firtool complains on field access
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,26 @@ | ||
| package memories | ||
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| import chisel3._ | ||
| import chisel3.util.log2Ceil | ||
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| class MemIOBundle[T <: Data](depth: Int, t: T) extends Bundle { | ||
| val rdAddr = Input(UInt(log2Ceil(depth).W)) | ||
| val rdData = Output(t) | ||
| val wrEna = Input(Bool()) | ||
| val wrData = Input(t) | ||
| val wrAddr = Input(UInt(log2Ceil(depth).W)) | ||
| } | ||
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| /** A simple module for testing memories in Tywaves */ | ||
| class BlockMem[T <: Data](depth: Int, t: T) extends Module { | ||
| val io = IO(new MemIOBundle(depth, t)) | ||
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| val mem = SyncReadMem(depth, t) | ||
| io.rdData := mem.read(io.rdAddr) | ||
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| when(io.wrEna) { | ||
| mem.write(io.wrAddr, io.wrData) | ||
| } | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,84 @@ | ||
| package memories | ||
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| import org.scalatest.funspec.AnyFunSpec | ||
| import org.scalatest.matchers.must.Matchers | ||
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| import tywaves.simulator._ | ||
| import tywaves.simulator.simulatorSettings._ | ||
| import chisel3._ | ||
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| class BlockMemTest extends AnyFunSpec with Matchers { | ||
| describe("TywavesSimulator") { | ||
| import TywavesSimulator._ | ||
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| it("runs BlockMem of UInt8") { | ||
| val t = UInt(8.W) | ||
| simulate(new BlockMem(15, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_uint8")(dut => | ||
| dut.clock.step(2) | ||
| ) | ||
| } | ||
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| it("runs BlockMem of Bundle") { | ||
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| class ComplexElement extends Bundle { | ||
| val a = new Bundle { | ||
| val subA1 = UInt(8.W) | ||
| val subA2 = SInt(8.W) | ||
| } | ||
| val payload = Bits(8.W) | ||
| } | ||
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| val t = new ComplexElement | ||
| simulate( | ||
| new BlockMem(4, t), | ||
| Seq(VcdTrace, WithTywavesWaveforms(false), SaveWorkdirFile("workdir")), | ||
| simName = "runs_mem_bundle", | ||
| )(dut => dut.clock.step(2)) | ||
| } | ||
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| it("runs BlockMem of Vec") { | ||
| val t = Vec(4, UInt(8.W)) | ||
| simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_vec")(dut => | ||
| dut.clock.step(2) | ||
| ) | ||
| } | ||
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| it("runs BlockMem of Enum") { | ||
| object SelType extends ChiselEnum { val A, B, C = Value } | ||
| val t = SelType() | ||
| simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum")(dut => | ||
| dut.clock.step(2) | ||
| ) | ||
| } | ||
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| it("runs BlockMem of Enum in Bundle") { | ||
| object SelType extends ChiselEnum { val A, B, C = Value } | ||
| class ComplexElement extends Bundle { | ||
| val sel = SelType() | ||
| val payload = Bits(8.W) | ||
| } | ||
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| val t = new ComplexElement | ||
| simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_bundle")(dut => | ||
| dut.clock.step(2) | ||
| ) | ||
| } | ||
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| it("runs BlockMem of Enum in Vec") { | ||
| object SelType extends ChiselEnum { val A, B, C = Value } | ||
| val t = Vec(4, SelType()) | ||
| simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_vec")(dut => | ||
| dut.clock.step(2) | ||
| ) | ||
| } | ||
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| it("runs BlockMem of Enum in 2D-Vec") { | ||
| object SelType extends ChiselEnum { val A, B, C = Value } | ||
| val t = Vec(4, Vec(2, SelType())) | ||
| simulate(new BlockMem(4, t), Seq(VcdTrace, WithTywavesWaveforms(false)), simName = "runs_mem_enum_2d_vec")(dut => | ||
| dut.clock.step(2) | ||
| ) | ||
| } | ||
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| } | ||
| } |